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ORCIDJeffrey T. Draper
Jeffrey Draper – Jeff Draper
Person information
- affiliation: University of Southern California, Los Angeles, USA
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2010 – 2019
- 2019
[j13]Yang Zhang
, Ji Li, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel:
Yield modelling and analysis of bundled data and ring-oscillator based designs. IET Comput. Digit. Tech. 13(3): 262-272 (2019)- [j12]Ji Li, Zihao Yuan, Zhe Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Shahin Nazarian, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Normalization and dropout for stochastic computing-based deep convolutional neural networks. Integr. 65: 395-403 (2019) - [j11]Zhe Li, Ji Li, Ao Ren, Ruizhe Cai, Caiwen Ding, Xuehai Qian, Jeffrey Draper, Bo Yuan, Jian Tang, Qinru Qiu, Yanzhi Wang:
HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1543-1556 (2019) - 2018
- [c80]Raghav Mehta, Yuyang Huang, Mingxi Cheng, Shrey Bagga, Nishant Mathur, Ji Li, Jeffrey Draper, Shahin Nazarian:
High performance training of deep neural networks using pipelined hardware acceleration and distributed memory. ISQED 2018: 383-388 - [c79]Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing. ISVLSI 2018: 28-33 - [i2]Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing. CoRR abs/1805.04142 (2018) - 2017
- [j10]Ji Li, Jeffrey Draper:
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits. ACM Trans. Design Autom. Electr. Syst. 22(3): 57:1-57:21 (2017) - [c78]Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang:
Structural design optimization for deep convolutional neural networks using stochastic computing. DATE 2017: 250-253 - [c77]Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang:
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. ACM Great Lakes Symposium on VLSI 2017: 427-430 - [c76]Zihao Yuan, Ji Li, Zhe Li, Caiwen Ding, Ao Ren, Bo Yuan, Qinru Qiu, Jeffrey Draper, Yanzhi Wang:
Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks. ACM Great Lakes Symposium on VLSI 2017: 467-470 - [c75]Ji Li, Zihao Yuan, Zhe Li, Caiwen Ding, Ao Ren, Qinru Qiu, Jeffrey Draper, Yanzhi Wang:
Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks. IJCNN 2017: 1230-1236 - [i1]Ji Li, Zihao Yuan, Zhe Li, Caiwen Ding, Ao Ren, Qinru Qiu, Jeffrey T. Draper, Yanzhi Wang:
Hardware-Driven Nonlinear Activation for Stochastic Computing Based Deep Convolutional Neural Networks. CoRR abs/1703.04135 (2017) - 2016
- [j9]Lihang Zhao, Lizhong Chen, Woojin Choi, Jeffrey T. Draper:
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution. ACM Trans. Archit. Code Optim. 12(4): 51:1-51:26 (2016) - [c74]Ji Li, Jeffrey Draper:
Accelerating soft-error-rate (SER) estimation in the presence of single event transients. DAC 2016: 55:1-55:6 - [c73]Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper:
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. FPGA 2016: 205-214 - [c72]Ji Li, Jeffrey T. Draper:
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements. ISVLSI 2016: 737-742 - [c71]Aditya M. Deshpande, Jeffrey T. Draper:
A New Metric to Measure Cache Utilization for HPC Workloads. MEMSYS 2016: 10-17 - 2015
- [c70]Gopi Neela, Jeffrey Draper:
Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC. 3DIC 2015: TS8.23.1-TS8.23.6 - [c69]Aditya M. Deshpande, Jeffrey T. Draper:
Modeling Data Movement in the Memory Hierarchy in HPC Systems. MEMSYS 2015: 158-161 - [c68]Aditya M. Deshpande, Jeffrey T. Draper, J. Brian Rigdon, Richard F. Barrett:
PathFinder: a signature-search miniapp and its runtime characteristics. IA3@SC 2015: 9:1-9:4 - 2014
- [j8]Fatemeh Kashfi, Jeff Draper:
Thermal sensor allocation for 3DICs using three dimensional thermal sensors. Microelectron. J. 45(5): 500-507 (2014) - [c67]Lihang Zhao, Jeffrey T. Draper:
Consolidated conflict detection for hardware transactional memory. PACT 2014: 201-212 - [c66]Lihang Zhao, Lizhong Chen, Jeffrey T. Draper:
Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory. IPDPS 2014: 605-614 - [c65]Neela Gopi, Jeffrey Draper:
Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC. ISCAS 2014: 802-805 - [c64]Neela Gopi, Jeffrey Draper:
Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach. ISVLSI 2014: 154-159 - [c63]Gopi Neela, Jeffrey Draper:
A multi-mode energy-efficient double-precision floating-point multiplier. MWSCAS 2014: 29-32 - [c62]David S. Lee, Jeffrey Draper:
A framework to quantify FPGA design hardness against radiation-induced single event effects. MWSCAS 2014: 302-305 - 2013
- [j7]Woojin Choi, Jeffrey T. Draper:
Improving Utilization of Hardware Signatures in Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(11): 2230-2239 (2013) - [c61]Neela Gopi, Jeffrey Draper:
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC. 3DIC 2013: 1-6 - [c60]Fatemeh Kashfi, Jeff Draper:
Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs. DSD 2013: 404-411 - [c59]Neela Gopi, Jeffrey Draper:
An asymmetric adaptive-precision energy-efficient 3DIC multiplier. ACM Great Lakes Symposium on VLSI 2013: 269-274 - [c58]Lihang Zhao, Woojin Choi, Lizhong Chen, Jeffrey T. Draper:
In-network traffic regulation for Transactional Memory. HPCA 2013: 520-531 - [c57]Lihang Zhao, Jeff Draper:
Implementation of hybrid version management in hardware transactional memory. ISCAS 2013: 777-780 - [c56]Neela Gopi, Jeffrey Draper:
Logic-on-logic partitioning techniques for 3-dimensional integrated circuits. ISCAS 2013: 789-792 - [c55]Aditya M. Deshpande, Jeffrey Draper:
Leakage energy estimates for HPC applications. E2SC@SC 2013: 5:1-5:8 - 2012
- [c54]Lihang Zhao, Woojin Choi, Jeffrey T. Draper:
TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency. PACT 2012: 439-440 - [c53]Woojin Choi, Lihang Zhao, Jeff Draper:
Mileage-based contention management in transactional memory. PACT 2012: 471-472 - [c52]Lihang Zhao, Woojin Choi, Jeff Draper:
SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory. IPDPS 2012: 95-106 - [c51]Lihang Zhao, Jeff Draper:
On the Correctness of Mixing Lazy and Eager Version Management in Transactions. IPDPS Workshops 2012: 2534-2537 - [c50]Aditya M. Deshpande, Jeffrey Draper:
Comparing squaring and cubing units with multipliers. MWSCAS 2012: 466-469 - [c49]Gopi Neela, Jeffrey Draper:
Challenges in 3DIC implementation of a design using current CAD tools. MWSCAS 2012: 478-481 - [c48]Fatemeh Kashfi, Jeff Draper:
Thermal sensor design for 3D ICs. MWSCAS 2012: 482-485 - 2011
- [c47]Woojin Choi, Jeff Draper:
Unified Signatures for Improving Performance in Transactional Memory. IPDPS 2011: 817-827 - 2010
- [c46]Bilal Zafar, Jeff Draper, Timothy Mark Pinkston:
Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip. ICPP 2010: 443-452 - [c45]Woojin Choi, Jeff Draper:
Locality-aware adaptive grain signatures for Transactional Memories. IPDPS 2010: 1-10 - [c44]Woojin Choi, Young Hoon Kang, Taek-Jun Kwon, Jeff Draper:
Implementation of adaptive grain signatures for transactional memories. ISCAS 2010: 3489-3492 - [c43]Mahta Haghi, Jeff Draper:
A single-event upset hardening technique for high speed MOS Current Mode Logic. ISCAS 2010: 4137-4140 - [c42]Young Hoon Kang, Taek-Jun Kwon, Jeffrey T. Draper:
Fault-Tolerant Flow Control in On-chip Networks. NOCS 2010: 79-86
2000 – 2009
- 2009
- [j6]Taek-Jun Kwon, Jeffrey T. Draper:
Floating-point division and square root using a Taylor-series expansion algorithm. Microelectron. J. 40(11): 1601-1605 (2009) - [c41]Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper:
Multicast routing with dynamic packet fragmentation. ACM Great Lakes Symposium on VLSI 2009: 113-116 - [c40]Mahta Haghi, Jeff Draper:
The effect of design parameters on single-event upset sensitivity of MOS current mode logic. ACM Great Lakes Symposium on VLSI 2009: 233-238 - [c39]Young Hoon Kang, Taek-Jun Kwon, Jeff Draper:
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers. NOCS 2009: 250-255 - 2008
- [c38]Riaz Naseer, Jeff Draper:
Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. ESSCIRC 2008: 222-225 - [c37]Riaz Naseer, Jeff Draper:
DEC ECC design to improve memory reliability in Sub-100nm technologies. ICECS 2008: 586-589 - [c36]Taek-Jun Kwon, Jeff Sondeen, Jeff Draper:
Floating-point division and square root implementation using a Taylor-series expansion algorithm. ICECS 2008: 702-705 - 2007
- [c35]Sumit D. Mediratta, Jeffrey T. Draper:
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router. ASAP 2007: 69-75 - [c34]Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski:
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology. ACM Great Lakes Symposium on VLSI 2007: 227-230 - [c33]Sumit D. Mediratta, Jeffrey T. Draper:
Characterization of a Fault-tolerant NoC Router. ISCAS 2007: 381-384 - [c32]Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski:
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. ISCAS 2007: 1879-1882 - 2006
- [c31]Rashed Zafar Bhatti, Monty Denneau, Jeff Draper:
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ACM Great Lakes Symposium on VLSI 2006: 198-203 - [c30]Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper:
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability. ISCAS 2006 - [c29]Rashed Zafar Bhatti, Monty Denneau, Jeff Draper:
Phase measurement and adjustment of digital signals using random sampling technique. ISCAS 2006 - [c28]Riaz Naseer, Jeff Draper:
DF-DICE: a scalable solution for soft error tolerant circuit design. ISCAS 2006 - 2005
- [j5]Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca:
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. J. VLSI Signal Process. 40(1): 73-84 (2005) - [c27]Sumit D. Mediratta, Jeffrey T. Draper:
Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System. HiPC 2005: 407-419 - [c26]Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen, Jeffrey T. Draper:
An area-efficient and protected network interface for processing-in-memory systems. ISCAS (3) 2005: 2951-2954 - [c25]Taek-Jun Kwon, Jeff Sondeen, Jeffrey T. Draper:
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems. ISCAS (4) 2005: 3331-3334 - 2004
- [c24]Taek-Jun Kwon, Joong-Seok Moon, Jeff Sondeen, Jeffrey T. Draper:
A 0.18 µm implementation of a floating-point unit for a processing-in-memory system. ISCAS (2) 2004: 453-456 - [c23]Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Draper:
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. VLSI Design 2004: 863-868 - 2003
- [j4]Joong-Seok Moon, William C. Athas, Sigfrid D. Soli, Jeffrey T. Draper, Peter A. Beerel:
Voltage-pulse driven harmonic resonant rail drivers for low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 762-777 (2003) - [c22]Joong-Seok Moon, Taek-Jun Kwon, Jeff Sondeen, Jeffrey Draper:
An area-efficient standard-cell floating-point unit design for a processing-in-memory system. ESSCIRC 2003: 57-60 - 2002
- [c21]Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim:
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. ASAP 2002: 163-172 - [c20]Joong-Seok Moon, William C. Athas, Peter A. Beerel, Jeffrey T. Draper:
Low-power sequential access memory design. CICC 2002: 111-114 - [c19]Jeffrey T. Draper, Jacqueline Chame, Mary W. Hall, Craig S. Steele, Tim Barrett, Jeff LaCoss, John J. Granacki, Jaewook Shin, Chun Chen, Chang Woo Kang, Ihn Kim Gokhan:
The architecture of the DIVA processing-in-memory chip. ICS 2002: 14-25 - 2001
- [c18]Herming Chiueh, Jeffrey Draper, John Choma Jr.:
A dynamic thermal management circuit for system-on-chip designs. ICECS 2001: 577-580 - 2000
- [c17]Louis Luh, John Choma Jr., Jeffrey Draper:
A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes. ISCAS 2000: 65-68 - [c16]Louis Luh, John Choma Jr., Jeffrey Draper:
Performance optimization for high-order continuous-time ΣΔ modulators with extra loop delay. ISCAS 2000: 669-672
1990 – 1999
- 1999
- [c15]Louis Luh, John Choma Jr., Jeffrey T. Draper:
Area-Efficient Area Pad Design for High Pin-Count Chips. Great Lakes Symposium on VLSI 1999: 78-81 - [c14]Louis Luh, John Choma Jr., Jeffrey Draper:
A high-speed high-resolution CMOS current comparator. ICECS 1999: 303-306 - [c13]Louis Luh, John Choma Jr., Jeffrey Draper:
Feed-forward gain compensation for CMOS continuous-time ΣΔ modulators. ICECS 1999: 1685-1688 - [c12]Louis Luh, John Choma Jr., Jeffrey T. Draper:
A self-sensing tristate pad driver for control signals of multiple bus controllers. ISCAS (1) 1999: 447-450 - [c11]Mary W. Hall, Peter M. Kogge, Jefferey G. Koller, Pedro C. Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John J. Granacki, Jay B. Brockman, Apoorv Srivastava, William C. Athas, Vincent W. Freeh, Jaewook Shin, Joonseok Park:
Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture. SC 1999: 57 - 1998
- [c10]Louis Luh, John Choma Jr., Jeffrey T. Draper:
A Continuous-Time Switched-Current Sigma-Delta Modulator with Reduced Loop Delay. Great Lakes Symposium on VLSI 1998: 286- - [c9]Louis Luh, John Choma Jr., Jeffrey Draper:
A high-speed fully differential current switch. ICECS 1998: 343-346 - [c8]Louis Luh, John Choma Jr., Jeffrey Draper:
A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application. ICECS 1998: 347-350 - [c7]Jeffrey T. Draper, Jay Block, Jeff Koller, Craig S. Steele:
Thermal Management in Embedded Systems Using MEMS. IPPS/SPDP Workshops 1998: 900-901 - [c6]Craig S. Steele, Jeffrey T. Draper, Jeff Koller:
Safety Net: Secure Communications for Embedded High-Performance Computing. IPPS/SPDP Workshops 1998: 908-912 - 1997
- [c5]Craig S. Steele, Jeffrey T. Draper, Jeff Koller, C. LaCour:
A Bus-Efficient Low-Latency Network Interface for the PDSS Multicomputer. HPDC 1997: 213-222 - [c4]Jeffrey T. Draper, Fabrizio Petrini:
Routing in Bidirectional k-ary n-cubes with the Red Rover Algorithm. PDPTA 1997: 1184-1193 - 1996
- [c3]Jeffrey T. Draper:
The Red Rover Algorithm for Deadlock-Free Routing on Bidirectional Rings. PDPTA 1996: 345-354 - 1994
- [j3]Jeffrey T. Draper, Joydeep Ghosh:
A Comprehensive Analytical Model for Wormhole Routng in Multicomputer Systems. J. Parallel Distributed Comput. 23(2): 202-214 (1994) - [j2]Jeffrey T. Draper, Joydeep Ghosh:
The M-Cache: A Message-Handling Mechanism for Multicomputer Systems. Parallel Comput. 20(9): 1269-1288 (1994) - 1993
- [j1]Joydeep Ghosh, Kelvin D. Goveas, Jeffrey T. Draper:
Performance Evaluation of a Parallel I/O Subsystem for Hypercube Multicomputers. J. Parallel Distributed Comput. 17(1-2): 90-106 (1993) - 1992
- [c2]Jeffrey T. Draper, Joydeep Ghosh:
Multipath E-Cube Algorithms (MECA) for Adaptive Wormhole Routing and Broadcasting in itk-ary itn-Cubes. IPPS 1992: 407-410 - 1991
- [c1]Jeffrey T. Draper, Joydeep Ghosh, William C. Athas:
The M-cache: a message-retrieving mechanism for multicomputer systems. SPDP 1991: 258-265
Coauthor Index
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