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ORCIDGopi Neela
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- affiliation: University of Southern California, Information Sciences Institute, Los Angeles, USA
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2010 – 2019
- 2019
[c10]Dipan Kumar Mandal, Srivatsava Jandhyala, Om Ji Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney
, Lance Hacking, Jim Radford, Eagle Jones, Belliappa Kuttanna, Hong Wang:
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. DATE 2019: 960-963- 2015
- [c9]Gopi Neela, Jeffrey Draper:
Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC. 3DIC 2015: TS8.23.1-TS8.23.6 - 2014
- [c8]Neela Gopi, Jeffrey Draper:
Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC. ISCAS 2014: 802-805 - [c7]Neela Gopi, Jeffrey Draper:
Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach. ISVLSI 2014: 154-159 - [c6]Gopi Neela, Jeffrey Draper:
A multi-mode energy-efficient double-precision floating-point multiplier. MWSCAS 2014: 29-32 - 2013
- [c5]Neela Gopi, Jeffrey Draper:
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC. 3DIC 2013: 1-6 - [c4]Neela Gopi, Jeffrey Draper:
An asymmetric adaptive-precision energy-efficient 3DIC multiplier. ACM Great Lakes Symposium on VLSI 2013: 269-274 - [c3]Neela Gopi, Jeffrey Draper:
Logic-on-logic partitioning techniques for 3-dimensional integrated circuits. ISCAS 2013: 789-792 - 2012
- [c2]Gopi Neela, Jeffrey Draper:
Challenges in 3DIC implementation of a design using current CAD tools. MWSCAS 2012: 478-481
2000 – 2009
- 2006
- [c1]Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas:
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. AICCSA 2006: 88-92
Coauthor Index
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