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ORCIDIntegration, Volume 65
Volume 65, March 2019
- Thawra Kadeed
, Sebastian Tobuschat, Adam Kostrzewa, Rolf Ernst:
Safe and efficient power management of hard real-time networks-on-chip. 1-17 - Sasan Nikseresht, Seyed Javad Azhari:
A new current-mode computational analog block free from the body-effect. 18-31 - Victor Hugo Carbajal-Gomez, Esteban Tlelo-Cuautle, Jesús M. Muñoz-Pacheco, Luis Gerardo de la Fraga, Carlos Sánchez-López, Francisco Vidal Fernández Fernández:
Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED. 32-42 - Kanika, R. Sankara Prasad, Nitin Chaturvedi, S. Gurunarayanan:
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications. 43-50 - Sarang Kazeminia:
A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs. 51-73 - R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra:
All MOS noise-shaped time-mode temperature sensor. 74-80 - Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez:
A tool for the automatic generation and analysis of regular analog layout modules. 81-87 - Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita:
Data-path aware high-level ECO synthesis. 88-96 - Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King:
FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems. 97-103 - Zahra Shirmohammadi:
OP-Fibo: An efficient Forbidden Pattern Free CAC design. 104-109 - Anthony G. Scanlan:
Low power & mobile hardware accelerators for deep convolutional neural networks. 110-127 - Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi:
Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing. 128-137 - Puneeth Kumar, S. Rekha:
Fast start crystal oscillator design with negative resistance control. 138-148 - Sherif F. Nafea, Ahmed A. S. Dessouki, S. El-Rabaie, Basem E. Elnaghi, Yehea Ismail, Hassan Mostafa:
An accurate model of domain-wall-based spintronic memristor. 149-162 - Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Design of quadruple precision multiplier architectures with SIMD single and double precision support. 163-174 - Manas Kumar Hati, Tarun Kanti Bhattacharyya:
A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation. 175-188 - Tram Thi Bao Nguyen, Hanho Lee:
Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications. 189-200
- Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. 201-210 - Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira:
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI. 211-218 - Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel techniques for memristive multifunction logic design. 219-230 - Ahmad N. Abdulfattah, Charalampos C. Tsimenidis, Alex Yakovlev:
Ultra-low power m-sequence code generator for body sensor node applications. 231-240 - Teng Xu, Miodrag Potkonjak:
Circuit power optimization using pipelining and dual-supply voltage assignment. 241-251 - Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano:
Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores. 252-262
- Lawrence T. Clark, James Adams, Keith E. Holbert:
Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory. 263-272 - Hongyu An, M. Amimul Ehsan, Zhen Zhou, Fangyang Shen, Yang Yi:
Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons. 273-281 - Dongjin Lee, Sourav Das, Partha Pratim Pande:
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture. 282-292 - Soheil Salehi, Navid Khoshavi, Ramtin Zand, Ronald F. DeMara:
Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture. 293-307
- Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu:
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. 308-321 - Leilei Wang, Cheng Zhuo, Pingqiang Zhou:
Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips. 322-330 - Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen:
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems. 331-343 - Xiangwei Cai, Jieming Yin, Pingqiang Zhou:
An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems. 344-350 - Wei Gao, Zhiliang Qian, Pingqiang Zhou:
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation. 351-361
- Cheng Zhuo, Baixin Chen:
System-level design consideration and optimization of through-silicon-via inductor. 362-369 - Junjun Hu, Zhijing Li, Meng Yang, Zixin Huang, Weikang Qian:
A high-accuracy approximate adder with correct sign calculation. 370-388 - Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li:
Exploiting distribution of unknown values in test responses to optimize test output compactors. 389-394
- Ji Li, Zihao Yuan, Zhe Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Shahin Nazarian, Qinru Qiu, Bo Yuan, Yanzhi Wang:
Normalization and dropout for stochastic computing-based deep convolutional neural networks. 395-403 - Sebastian Tobuschat, Adam Kostrzewa, Rolf Ernst:
Selective congestion control for mixed-critical networks-on-chip. 404-416 - Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, Song Chen:
High throughput hardware architecture for accurate semi-global matching. 417-427 - Varsha Agarwal, Ananya Singla, Mahammad Samiuddin, Sudip Roy, Tsung-Yi Ho, Indranil Sengupta, Bhargab B. Bhattacharya:
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips. 428-443 - Omayma Matoussi, Frédéric Pétrot:
Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation. 444-454
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