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ORCID19th HPCA 2013: Shenzhen, China
- 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5585-8
- Emily R. Blem, Jaikrishnan Menon, Karthikeyan Sankaralingam:
Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. 1-12 - Yuhao Zhu, Vijay Janapa Reddi:
High-performance and energy-efficient mobile web browsing on big/little systems. 13-24 - Yebin Lee, Soontae Kim
, Seokin Hong, Jongmin Lee:
Skinflint DRAM system: Minimizing DRAM chip writes for low power. 25-34 - Chao Li, Ruijin Zhou, Tao Li:
Enabling distributed generation powered sustainable high-performance data center. 35-46 - Furat Afram, Hui Zeng, Kanad Ghose:
A group-commit mechanism for ROB-based processors implementing the X86 ISA. 47-58 - Muhammad Umar Farooq, Khubaib, Lizy K. John:
Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches. 59-70 - James Bonanno, Adam Collura, Daniel Lipetz, Ulrich Mayer, Brian R. Prasky, Anthony Saporito:
Two level bulk preload branch prediction. 71-82 - Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, Andreas Moshovos:
RECAP: A region-based cure for the common cold (cache). 83-94 - Marisabel Guevara, Benjamin Lubin, Benjamin C. Lee:
Navigating heterogeneous processors with market mechanisms. 95-106 - Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi:
Application-to-core mapping policies to reduce memory system interference in multi-core systems. 107-118 - Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jiménez:
Improving multi-core performance using mixed-cell cache architecture. 119-130 - Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Junghee Lee, Jongman Kim:
ECM: Effective Capacity Maximizer for high-performance compressed caching. 131-142 - Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob:
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. 143-154 - Andreas Sandberg, Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Modeling performance variation due to cache sharing. 155-166 - Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian:
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. 167-178 - Rui Hou, Tao Jiang, Liuhang Zhang, Pengfei Qi, Jianbo Dong, Haibin Wang, Xiongli Gu, Shujie Zhang:
Cost effective data center servers. 179-187 - Lingjia Tang, Jason Mars, Xiao Zhang, Robert Hagmann, Robert Hundt, Eric Tune:
Optimizing Google's warehouse scale computers: The NUMA experience. 188-197 - Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu:
Runnemede: An architecture for Ubiquitous High-Performance Computing. 198-209 - Zhongqi Li, Ruijin Zhou, Tao Li:
Exploring high-performance and energy proportional interface for phase change memory systems. 210-221 - Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin:
Coset coding to extend the lifetime of memory. 222-233 - Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. 234-245 - Yubin Xia, Yutao Liu, Haibo Chen:
Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks. 246-257 - Mehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry Ponomarev, Nael B. Abu-Ghazaleh:
SCRAP: Architecture for signature-based protection from Code Reuse Attacks. 258-269 - Xun Jian, Rakesh Kumar:
Adaptive Reliability Chipkill Correct (ARCC). 270-281 - Jianhui Yue, Yifeng Zhu:
Accelerating write by exploiting PCM asymmetries. 282-293 - Neal Clayton Crago, Omid Azizi, Steven S. Lumetta, Sanjay J. Patel:
Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors. 294-305 - Jia Rao, Kun Wang, Xiaobo Zhou, Cheng-Zhong Xu:
Optimizing virtual machine scheduling in NUMA multicore systems. 306-317 - Richard Sampson, Ming Yang, Siyuan Wei, Chaitali Chakrabarti, Thomas F. Wenisch:
Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound. 318-329 - Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
Power-efficient computing for compute-intensive GPGPU applications. 330-341 - Nilanjan Goswami, Bingyi Cao, Tao Li:
Power-performance co-optimization of throughput core architecture using resistive memory. 342-353 - Daniel Lustig, Margaret Martonosi:
Reducing GPU offload latency via fine-grained CPU-GPU synchronization. 354-365 - Lizhong Chen, Timothy Mark Pinkston:
Worm-Bubble Flow Control. 366-377 - Tushar Krishna, Chia-Hsin Owen Chen, Woo-Cheol Kwon, Li-Shiuan Peh:
Breaking the on-chip latency barrier using SMART. 378-389 - Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King:
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. 390-399 - Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas:
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. 400-411 - Mohammad Abdel-Majeed, Murali Annavaram:
Warped register file: A power efficient register file for GPGPUs. 412-423 - Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, Benjamin C. Lee:
Disintegrated control for energy-efficient and heterogeneous memory systems. 424-435 - Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke:
Illusionist: Transforming lightweight cores into aggressive cores on demand. 436-447 - Ehsan K. Ardestani, Jose Renau:
ESESC: A fast multicore simulator using Time-Based Sampling. 448-459 - Behnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Madhu Saravana Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, Stephen W. Keckler:
How to implement effective prediction and forwarding for fusable dynamic multicore architectures. 460-471 - Andrew Nere, Atif Hashmi, Mikko H. Lipasti, Giulio Tononi:
Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons. 472-483 - Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova:
Layout-conscious random topologies for HPC off-chip interconnects. 484-495 - Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge:
Scaling towards kilo-core processors with asymmetric high-radix topologies. 496-507 - Ahmad Samih, Ren Wang, Anil Krishna, Christian Maciocco, Tsung-Yuan Charlie Tai, Yan Solihin:
Energy-efficient interconnect via Router Parking. 508-519 - Lihang Zhao, Woojin Choi, Lizhong Chen, Jeffrey T. Draper:
In-network traffic regulation for Transactional Memory. 520-531 - Tayyeb Mahmood, Soontae Kim, Seokin Hong:
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling. 532-541 - Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas:
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. 542-553 - Xuehai Qian, He Huang, Benjamín Sahelices, Depei Qian:
Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model. 554-565 - Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte:
High-speed formal verification of heterogeneous coherence hierarchies. 566-577 - Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, Tor M. Aamodt:
Cache coherence for GPU architectures. 578-590 - Minsoo Rhu, Mattan Erez:
The dual-path execution model for efficient GPU control flow. 591-602 - Yaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang, Wei Liu, Xi Ning:
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments. 603-614 - Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-latency DRAM: A low latency and low cost DRAM architecture. 615-626 - Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
A case for Refresh Pausing in DRAM memory systems. 627-638 - Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu:
MISE: Providing performance predictability and improving fairness in shared main memory systems. 639-650
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