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ORCIDMasayoshi Yoshimura
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2020 – today
- 2024
[j6]Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa:
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 583-591 (2024)- 2023
- [c29]Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura:
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. DFT 2023: 1-6 - [c28]Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. DFT 2023: 1-6 - [c27]Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura:
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. DFT 2023: 1-6 - 2022
- [c26]Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa:
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. DFT 2022: 1-6 - 2020
- [c25]Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. DFT 2020: 1-6 - [c24]Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai:
A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. IOLTS 2020: 1-4
2010 – 2019
- 2019
- [c23]Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai:
A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. DFT 2019: 1-6 - [c22]Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa:
A State Assignment Method to Improve Transition Fault Coverage for Controllers. DFT 2019: 1-4 - [c21]Yusuke Matsunaga, Masayoshi Yoshimura:
An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS 2019: 44-47 - [c20]Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura:
A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. IOLTS 2019: 293-298 - 2018
- [c19]Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS 2018: 43-46 - [c18]Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura:
A Capture Safe Static Test Compaction Method Based on Don't Cares. IOLTS 2018: 195-200 - [c17]Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura:
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. IOLTS 2018: 228-231 - 2017
- [j5]Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa:
A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2824-2833 (2017) - [c16]Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura:
Controller augmentation and test point insertion at RTL for concurrent operational unit testing. IOLTS 2017: 17-20 - [c15]Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa:
A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. PRDC 2017: 221-222 - 2015
- [c14]Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa:
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. ATS 2015: 13-18 - 2013
- [j4]Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura:
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. IEICE Trans. Inf. Syst. 96-D(9): 1994-2002 (2013) - [j3]Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga:
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6: 127-134 (2013) - [c13]Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura:
A don't care identification method for test compaction. DDECS 2013: 215-218 - [c12]Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa:
A smart Trojan circuit and smart attack method in AES encryption circuits. DFTS 2013: 278-283 - 2012
- [j2]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. 7(2): 593-600 (2012) - [j1]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 63-70 (2012) - [c11]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - [c10]Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami:
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC 2012: 213-218 - 2011
- [c9]Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT 2011: 268-276 - [c8]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - 2010
- [c7]Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki:
Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS 2010: 273-276
2000 – 2009
- 2006
- [c6]Masayoshi Yoshimura, Yusuke Matsunaga:
Development of practical ATPG tool with flexible interface. ATS 2006: 129 - 2005
- [c5]Masayoshi Yoshimura:
Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage. System Modelling and Optimization 2005: 181-191 - 2004
- [c4]Atsushi Kitazawa, Masayoshi Yoshimura:
SemanticObjects and Biomedical Informatics. BIBE 2004: 497-502 - 2002
- [c3]Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta:
A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium 2002: 298-304 - [c2]Masayoshi Yoshimura:
Collaborative optimization for product design and manufacturing. CAD 2002: 1-16 - 2001
- [c1]Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta:
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC 2001: 485-491
Coauthor Index
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