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ORCIDKatsuyoshi Miura
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2010 – 2019
- 2018
[j8]Katsuyoshi Miura, Atsuki Seko, Koji Nakamae:
Simulation-based evaluation of probing attacks to arbiter PUFs using a time-resolved emission microscope. Microelectron. Reliab. 88-90: 360-364 (2018)- 2017
- [c4]Koyo Suzuki, Katsuyoshi Miura, Koji Nakamae:
NBTI/PBTI tolerant arbiter PUF circuits. IOLTS 2017: 80-84 - 2011
- [j7]Kiyoshi Nikawa, Masatsugu Yamashita, Toru Matsumoto, Katsuyoshi Miura, Yoshihiro Midoh, Koji Nakamae:
The combinational or selective usage of the laser SQUID microscope, the non-bias laser terahertz emission microscope, and fault simulations in non-electrical-contact fault localization. Microelectron. Reliab. 51(9-11): 1624-1631 (2011)
2000 – 2009
- 2009
- [j6]Kiyoshi Nikawa, Shoji Inoue, Tatsuoki Nagaishi, Toru Matsumoto, Katsuyoshi Miura, Koji Nakamae:
New Approach of Laser-SQUID Microscopy to LSI Failure Analysis. IEICE Trans. Electron. 92-C(3): 327-333 (2009) - [j5]Masatsugu Yamashita, Chiko Otani
, Sunmi Kim, Hironaru Murakami, Masayoshi Tonouchi, Toru Matsumoto, Yoshihiro Midoh, Katsuyoshi Miura, Koji Nakamae, Kiyoshi Nikawa:
Laser THz emission microscope as a novel tool for LSI failure analysis. Microelectron. Reliab. 49(9-11): 1116-1126 (2009) - 2003
- [j4]Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka:
A low energy FIB processing, repair, and test system. Microelectron. Reliab. 43(9-11): 1627-1631 (2003) - 2002
- [j3]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
CAD navigation system, for backside waveform probing of CMOS devices. Microelectron. Reliab. 42(9-11): 1679-1684 (2002) - 2001
- [j2]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Development of an EB/FIB Integrated Test System. Microelectron. Reliab. 41(9-10): 1489-1494 (2001)
1990 – 1999
- 1999
- [c3]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Intelligent EB Test System for Automatic VLSI Fault Tracing. Asian Test Symposium 1999: 335-341 - 1997
- [j1]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electron. Test. 10(3): 255-269 (1997) - [c2]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. ASP-DAC 1997: 329-332 - [c1]Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka:
Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. Asian Test Symposium 1997: 162-167
Coauthor Index
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