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Journal Articles
- 2022
[j15]Davide Rossi
, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits 57(1): 127-139 (2022)- 2020
- [j14]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. Integr. 72: 194-207 (2020) - 2019
- [j13]Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini:
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits 54(7): 1970-1981 (2019) - 2018
- [j12]Michele Magno, Ali Ibrahim, Antonio Pullini, Maurizio Valle, Luca Benini:
An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding. J. Low Power Electron. 14(1): 101-109 (2018) - [j11]Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini:
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1094-1098 (2018) - 2017
- [j10]Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse:
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34(6): 46-53 (2017) - [j9]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j8]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2481-2494 (2017) - [j7]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2700-2713 (2017) - 2016
- [j6]Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini:
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. 84(3): 339-354 (2016) - 2012
- [j5]Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini:
Row-based FBB: A design-time optimization for post-silicon tunable circuits. Microelectron. J. 43(7): 456-465 (2012) - 2011
- [j4]Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - 2008
- [j3]David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli:
Network-on-Chip design and synthesis outlook. Integr. 41(3): 340-359 (2008) - 2007
- [j2]Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini:
Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007) - [j1]Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1297-1310 (2007)
Conference and Workshop Papers
- 2021
- [c34]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE 2021: 701-706 - [c33]Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC 2021: 60-62 - 2019
- [c32]Mario Osta, Ali Ibrahim, Michele Magno, Manuel Eggimann, Antonio Pullini, Paolo Gastaldo, Maurizio Valle:
An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications. ISCAS 2019: 1-4 - 2018
- [c31]Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini:
GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP 2018: 1-4 - [c30]Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini:
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. ESSCIRC 2018: 274-277 - [c29]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. ISCAS 2018: 1- - 2017
- [c28]Michele Magno, Ali Ibrahim, Antonio Pullini, Maurizio Valle, Luca Benini:
Energy Efficient System for Tactile Data Decoding Using an Ultra-Low Power Parallel Platform. NGCAS 2017: 17-20 - [c27]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. PATMOS 2017: 1-8 - [c26]Antonio Pullini, Davide Rossi, Germain Haugou, Luca Benini:
μDMA: An autonomous I/O subsystem for IoT end-nodes. PATMOS 2017: 1-8 - [c25]Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini:
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. PATMOS 2017: 1-8 - 2016
- [c24]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c23]Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini:
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS 2016: 2910 - [c22]Antonio Pullini, Stefan Mach, Michele Magno, Luca Benini:
A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing. S-CUBE 2016: 29-40 - 2015
- [c21]Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini:
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium 2015: 1-39 - [c20]Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini:
Exploring architectural heterogeneity in intelligent vision systems. HPCA 2015: 1-12 - [c19]Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta:
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. VLSI-SoC 2015: 25-30 - 2014
- [c18]Sara S. Ghoreishizadeh, Cristina Boero, Antonio Pullini, Camilla Baj-Rossi, Sandro Carrara, Giovanni De Micheli:
Sub-mW reconfigurable interface IC for electrochemical sensing. BioCAS 2014: 232-235 - [c17]Sara S. Ghoreishizadeh, Tolga Yalçin, Antonio Pullini, Giovanni De Micheli, Wayne P. Burleson, Sandro Carrara:
A lightweight cryptographic system for implantable biosensors. BioCAS 2014: 472-475 - [c16]Francesco Conti, Antonio Pullini, Luca Benini:
Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform. CVPR Workshops 2014: 624-629 - [c15]Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini:
Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS 2014: 274-279 - 2010
- [c14]Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini:
Networks on Chips: from research to products. DAC 2010: 300-305 - [c13]Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini:
3D NoCs - Unifying inter & intra chip communication. ISCAS 2010: 3337-3340 - [c12]Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini:
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ISLPED 2010: 401-406 - 2009
- [c11]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii:
Physically clustered forward body biasing for variability compensation in nanometer CMOS design. DATE 2009: 154-159 - [c10]Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli:
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. DATE 2009: 616-621 - [c9]Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini:
A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC 2009: 379-382 - 2008
- [c8]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE 2008: 379-384 - [c7]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI 2008: 177-182 - [c6]Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764 - 2007
- [c5]Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504 - [c4]Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Timing-driven row-based power gating. ISLPED 2007: 104-109 - [c3]Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini:
NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282 - 2006
- [c2]Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli:
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. SoC 2006: 1-4 - 2005
- [c1]Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini:
Fault tolerance overhead in network-on-chip flow control schemes. SBCCI 2005: 224-229
Informal and Other Publications
- 2021
- [i5]Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR abs/2110.09101 (2021) - 2020
- [i4]Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. CoRR abs/2007.13667 (2020) - [i3]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR abs/2012.02973 (2020) - 2016
- [i2]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR abs/1608.08376 (2016) - [i1]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR abs/1612.05974 (2016)
Coauthor Index
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