"Timing-Error-Tolerant Network-on-Chip Design Methodology."

Rutuparna Tamhankar et al. (2007)

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DOI: 10.1109/TCAD.2007.891371

access: closed

type: Journal Article

metadata version: 2020-09-24

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Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1297-1310 (2007)

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