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2020 – today
- 2024
[j17]Fei Tan
, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak:
A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS. IEEE J. Solid State Circuits 59(2): 626-635 (2024)- [j16]Yuzhao Fu, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Minglei Zhang, Rui Paulo Martins, Pui-In Mak:
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. IEEE J. Solid State Circuits 59(9): 3021-3031 (2024) - [j15]Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak:
A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. IEEE J. Solid State Circuits 59(11): 3866-3876 (2024) - [j14]Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu:
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2554-2558 (2024) - [c12]Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin:
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. ISCAS 2024: 1-5 - [c11]Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak:
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM. ISSCC 2024: 330-332 - [c10]Guoqiang Xin, Fei Tan, Junde Li, Junren Chen, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak:
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization. MWSCAS 2024: 882-887 - 2023
- [j13]Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak:
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM. IEEE J. Solid State Circuits 58(11): 3020-3029 (2023) - [j12]Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 281-285 (2023) - [c9]Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. ISSCC 2023: 214-215 - 2022
- [j11]Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. IEEE J. Solid State Circuits 57(11): 3288-3297 (2022) - [j10]Lei Xuan, Ka-Fai Un, Chi-Seng Lam, Rui Paulo Martins:
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4003-4007 (2022) - [c8]Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. APCCAS 2022: 1-5 - [c7]Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. ISSCC 2022: 1-3 - 2021
- [j9]Jixuan Li, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3143-3147 (2021) - [c6]Jixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. A-SSCC 2021: 1-3 - 2020
- [j8]Ka-Fai Un, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Anding Zhu, Robert Bogdan Staszewski:
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 37-41 (2020)
2010 – 2019
- 2019
- [j7]Ka-Fai Un, Gengzhen Qi, Jun Yin, Shiheng Yang, Shupeng Yu, Chio-In Ieong, Pui-In Mak, Rui Paulo Martins:
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3307-3316 (2019) - 2018
- [j6]Changzhi Li, Ka-Fai Un, Pui-In Mak, Ying Chen, José Maria Muñoz-Ferreras, Zhi Yang, Roberto Gómez-García:
Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(2): 165-177 (2018) - [j5]Wei-Han Yu, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 14-25 (2018) - 2016
- [c5]Chak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter. ASP-DAC 2016: 3-4 - 2015
- [j4]Chak-Fong Cheang, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1025-1032 (2015) - 2013
- [j3]Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS. IEEE J. Solid State Circuits 48(9): 2078-2089 (2013) - [j2]Wei-Han Yu, Chak-Fong Cheang, Pui-In Mak, Weng-Fai Cheng, Ka-Fai Un, U-Wai Lok, Rui Paulo Martins:
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware. IEEE Trans. Circuits Syst. II Express Briefs 60-II(8): 462-466 (2013) - 2011
- [c4]Weng-Fai Cheng, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
A highly-linear ultra-wideband balun-LNA for cognitive radios. EUROCON 2011: 1-4 - 2010
- [j1]Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 970-981 (2010) - [c3]Miguel A. Martins, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit. ISCAS 2010: 1276-1279
2000 – 2009
- 2009
- [c2]Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners. ISCAS 2009: 433-436 - 2008
- [c1]Ka-Fai Un, Pui-In Mak, Rui Paulo da Silva Martins:
A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers. APCCAS 2008: 1360-1363
Coauthor Index
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