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Publication search results
found 54 matches
- 2011
- Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq:
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. 7(3): 328-340 (2011) - Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu:
Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits. J. Low Power Electron. 7(4): 573-584 (2011) - Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid:
An Automated Power Emulation Framework for Embedded Software - Detecting Power-Critical Code Regions and Optimizing Software-Induced Power Consumption Peaks. J. Low Power Electron. 7(2): 255-264 (2011) - Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski:
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. 7(4): 471-481 (2011) - Malal Bathily, Bruno Allard, Frederic Hasbani, Vincent Pinon:
Low-Power, Battery-Operated, Large-Bandwidth Analog Integrated DC/DC Step-Down Converters. J. Low Power Electron. 7(1): 49-60 (2011) - Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev:
Self-Timed SRAM for Energy Harvesting Systems. J. Low Power Electron. 7(2): 274-284 (2011) - Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang:
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. J. Low Power Electron. 7(1): 87-95 (2011) - Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing. J. Low Power Electron. 7(2): 285-293 (2011) - Laurent Bousquet, Fabio Cenni, Emmanuel Simeu:
Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks. J. Low Power Electron. 7(4): 541-551 (2011) - Svetozar S. Broussev, Nikolay T. Tchamov:
Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus. J. Low Power Electron. 7(2): 209-217 (2011) - Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii:
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. J. Low Power Electron. 7(1): 2-16 (2011) - Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian:
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. 7(4): 529-530 (2011) - Nitin Chandrachoodan, Shankar Balachandran:
24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electron. 7(4): 459 (2011) - Claas Cornelius, Frank Sill Torres, Dirk Timmermann:
Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits. J. Low Power Electron. 7(4): 552-561 (2011) - Basab Datta, Wayne P. Burleson:
Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies. J. Low Power Electron. 7(3): 403-419 (2011) - Md. Ibrahim Faisal, Zahra Jeddi, Esmaeil Amini, Magdy A. Bayoumi:
A Flexible Architecture for Finite Field Galois Fields(2m) Arithmetic Processor. J. Low Power Electron. 7(3): 314-327 (2011) - Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira:
Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing. J. Low Power Electron. 7(2): 185-198 (2011) - David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - J. Kevin Hicks, Dhireesha Kudithipudi:
Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization. J. Low Power Electron. 7(2): 172-184 (2011) - Miao Hu, Hai (Helen) Li, Yiran Chen, Xiaobin Wang:
Spintronic Memristor: Compact Model and Statistical Analysis. J. Low Power Electron. 7(2): 234-244 (2011) - Bruno Jacinto, Carlos Moreira, Marcelino B. Santos:
Digital Sliding Mode Control of DC-DC Buck Converters. J. Low Power Electron. 7(2): 218-233 (2011) - Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. 7(4): 502-515 (2011) - Jitendra Kanungo, S. Dasgupta:
An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design. J. Low Power Electron. 7(3): 381-392 (2011) - Bhanu Kapoor, Shireesh Verma:
Power Management Design and Verification. J. Low Power Electron. 7(1): 41-48 (2011) - Kyungseok Kim, Vishwani D. Agrawal:
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. J. Low Power Electron. 7(4): 460-470 (2011) - Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. 7(1): 29-40 (2011) - Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac:
Trading Accuracy for Power in a Multiplier Architecture. J. Low Power Electron. 7(4): 490-501 (2011) - Tapas Kumar Kundu, Kolin Paul:
Analyzing and Improving Performance and Energy Efficiency of Android. J. Low Power Electron. 7(4): 516-528 (2011) - Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. 7(2): 294-301 (2011) - René van Leuken:
Selected Articles from the PATMOS 2010 Workshop. J. Low Power Electron. 7(2): 254 (2011)
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