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Publication search results
found 36 matches
- 1994
- Magdy S. Abadir, Tony Ambler:
Introduction. J. Electron. Test. 5(2-3): 129-130 (1994) - Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy:
High Level Test Economics Advisor (Hi-TEA). J. Electron. Test. 5(2-3): 195-206 (1994) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(1): 5 (1994) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(2-3): 127 (1994) - Vishwani D. Agrawal:
A tale of two designs: the cheapest and the most economic. J. Electron. Test. 5(2-3): 131-135 (1994) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(4): 317 (1994) - Mathew Alexander, K. Sríhari, C. Robert Emerson:
Cost based surface mount PCB design evaluation. J. Electron. Test. 5(2-3): 229-238 (1994) - Fadi Y. Busaba, Parag K. Lala:
Self-checking combinational circuit design for single and unidirectional multibit error. J. Electron. Test. 5(1): 19-28 (1994) - Kanad Chakraborty, Pinaki Mazumder:
Technology and layout-related testing of static random-access memories. J. Electron. Test. 5(4): 347-365 (1994) - Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Energy minimization and design for testability. J. Electron. Test. 5(1): 57-66 (1994) - Dipanwita Roy Chowdhury, Indranil Sengupta, Parimal Pal Chaudhuri:
A class of two-dimensional cellular automata and their applications in random pattern testing. J. Electron. Test. 5(1): 67-82 (1994) - Bruce F. Cockburn:
Deterministic tests for detecting singleV-coupling faults in RAMs. J. Electron. Test. 5(1): 91-113 (1994) - Bruce F. Cockburn:
Tutorial on semiconductor memory testing. J. Electron. Test. 5(4): 321-336 (1994) - Brendan Davis:
Economic modeling of board test strategies. J. Electron. Test. 5(2-3): 157-169 (1994) - I. D. Dear, Chryssa Dislis, Anthony P. Ambler, J. H. Dick:
Test strategy planning using economic analysis. J. Electron. Test. 5(2-3): 137-155 (1994) - J. H. Dick, Erwin Trischler, Chryssa Dislis, Anthony P. Ambler:
Sensitivity analysis in economics based test strategy planning. J. Electron. Test. 5(2-3): 239-251 (1994) - Mounir Fares, Bozena Kaminska:
Fuzzy optimization models for analog test decisions. J. Electron. Test. 5(2-3): 299-305 (1994) - Ad J. van de Goor, Yervant Zorian:
Effective march algorithms for testing single-order addressed memories. J. Electron. Test. 5(4): 337-345 (1994) - O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis:
Zero aliasing ROM BIST. J. Electron. Test. 5(4): 377-388 (1994) - Arno Kunzmann, Frank Böhland:
Self-test of sequential circuits with deterministic test pattern sequences. J. Electron. Test. 5(2-3): 307-312 (1994) - Enrico Macii, Angelo Raffaele Meo:
A test generation program for sequential circuits. J. Electron. Test. 5(1): 115-119 (1994) - Amitava Majumdar, Sarma B. K. Vrudhula:
Techniques for estimating test length under random test. J. Electron. Test. 5(2-3): 285-297 (1994) - Pinaki Mazumder:
Guest editor's introduction. J. Electron. Test. 5(4): 319-320 (1994) - Steven D. Millman:
Improving quality: Yield versus test coverage. J. Electron. Test. 5(2-3): 253-261 (1994) - Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Incorporating testability considerations in high-level synthesis. J. Electron. Test. 5(1): 43-55 (1994) - Michael Nicolaidis, O. Kebichi, Vladimir Castro Alves:
Trade-offs in scan path and BIST implementations for RAMs. J. Electron. Test. 5(2-3): 273-283 (1994) - Slawomir Pilarski, André Ivanov, Tiko Kameda:
On minimizing aliasing in scan-based compaction. J. Electron. Test. 5(1): 83-90 (1994) - Shekar Rao, Bert Haskell, Ian Yee:
Trade-off analysis on cost and manufacturing technology of an electronic product: Case study. J. Electron. Test. 5(2-3): 219-228 (1994) - Christian von Reventlow:
Comparing quality assurance methods and the resulting design strategies: Experiences from complex designs. J. Electron. Test. 5(2-3): 269-272 (1994) - Kewal K. Saluja:
On-chip testing of random access memories. J. Electron. Test. 5(4): 367-376 (1994)
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