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Publication search results
found 85 matches
- 2004
- Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi:
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. DSD 2004: 611-614 - Soyeb Alli, Chris Bailey:
Compiler-Directed Dynamic Memory Disambiguation for Loop Structures. DSD 2004: 130-134 - Soyeb Alli, Chris Bailey:
A Mechanism for Implementing Precise Exceptions in Pipelined Processors. DSD 2004: 598-602 - Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
Scene Management Models and Overlap Tests for Tile-Based Rendering. DSD 2004: 424-431 - Imed Aouadi, Omar Hammami:
Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder. DSD 2004: 227-233 - Maria J. Avedillo, José M. Quintana:
A Threshold Logic Synthesis Tool for RTD Circuits. DSD 2004: 624-627 - Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam:
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. DSD 2004: 603-606 - Chris Bailey:
A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines. DSD 2004: 121-129 - Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland:
A Simple Micro-Threaded Data-Driven Processor. DSD 2004: 70-77 - Ivan Blunno, Guy Alain Narboni, Claudio Passerone:
An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. DSD 2004: 540-547 - Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke:
Cost-Efficient Implementation of Adaptive Finite State Machines. DSD 2004: 144-151 - Cao Cao, Bengt Oelmann:
Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design. DSD 2004: 363-370 - Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51 - Ricardo Chaves, Leonel Sousa:
{2n+1, sn+k, sn-1}: A New RNS Moduli Set Extension. DSD 2004: 210-217 - Chichyang Chen, Kuo-Sheng Cheng:
An Efficient Exponential Algorithm with Exponential Convergence Rate. DSD 2004: 548-555 - Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis:
A Static Low-Power, High-Performance 32-bit Carry Skip Adder. DSD 2004: 615-619 - Pasquale Ciao, Giulio Colavolpe, Luca Fanucci:
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder. DSD 2004: 174-181 - Abey Abraham Cohen:
Addressing architecture for Brain-like Massively Parallel Computers. DSD 2004: 594-597 - Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95 - Matthew D'Souza, Adam Postula:
Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme. DSD 2004: 579-586 - Daniel Dietterle, Jerzy Ryman, Kai F. Dombrowski, Rolf Kraemer:
Mapping of High-Level SDL Models to Efficient Implementations for TinyOS. DSD 2004: 402-406 - Radek Dobias, Hana Kubátová:
FPGA Based Design of the Railway's Interlocking Equipments. DSD 2004: 467-473 - Alexander V. Drozd, R. Al-Azzeh, J. V. Drozd, M. V. Lobachev:
The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data. DSD 2004: 416-423 - Abdel Ejnioui, Abdelhalim Alsharqawi:
Pipeline-Level Control of Self-Resetting Pipelines. DSD 2004: 342-349 - David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin:
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD 2004: 394-401 - Luca Fanucci, Riccardo Locatelli, Esa Petri:
VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers. DSD 2004: 182-189 - Görschwin Fey, Junhao Shi, Rolf Drechsler:
BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172 - Petr Fiser, Hana Kubátová:
Boolean Minimizer FC-Min: Coverage Finding Process. DSD 2004: 152-159 - Piotr Gawkowski, Janusz Sosnowski:
Evaluation of Transient Fault Susceptibility in Microprocessor Systems. DSD 2004: 432-439 - Vladimir Hahanov, Irina V. Hahanova, Stanley Hyduke:
Topological BDP Fault Simulation Method. DSD 2004: 440-443
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