"A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager ..."

Pasquale Ciao, Giulio Colavolpe, Luca Fanucci (2004)

Details and statistics

DOI: 10.1109/DSD.2004.1333274

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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