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ORCIDGwenolé Corre
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2020 – today
- 2023
[c12]Ali Hachem, Imane Belalchheb, Yoann Moline, Frédérick Carrel, Gwenolé Corre:
FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator. NorCAS 2023: 1-7- 2022
- [j2]Andréa Macario Barros
, Maugan Michel, Yoann Moline, Gwenolé Corre, Frédérick Carrel:
A Comprehensive Survey of Visual SLAM Algorithms. Robotics 11(1): 24 (2022)
2010 – 2019
- 2018
- [c11]Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement:
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. IPDPS Workshops 2018: 202-205 - 2017
- [c10]Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement:
Model-driven reliability evaluation for MPSoC design. DASIP 2017: 1-6 - 2016
- [c9]Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy:
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI 2016: 655-660 - 2014
- [c8]Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy:
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP 2014: 169-172 - [c7]Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy:
An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI 2014: 229-230
2000 – 2009
- 2008
- [j1]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques 27(1-2): 235-254 (2008) - 2006
- [i5]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power. CoRR abs/cs/0605142 (2006) - [i4]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006) - [i3]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
A Memory Aware High Level Synthesis Too. CoRR abs/cs/0605144 (2006) - [i2]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware High-Level Synthesis for Embedded Systems. CoRR abs/cs/0605145 (2006) - [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin:
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006) - 2005
- [c6]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) 2005: 61-64 - [c5]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683 - 2004
- [c4]Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin:
Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47 - [c3]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95 - [c2]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI 2004: 82-85 - [c1]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280
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