- Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 7: 1 (2014) - Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 110-118 (2014) - Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 27-36 (2014) - Jingcheng Zhuang, Robert Bogdan Staszewski
:
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. IPSJ Trans. Syst. LSI Des. Methodol. 7: 2-15 (2014) - 2013
- Amila Akagic, Hideharu Amano:
Design and Implementation of IP-based iSCSI Offload Engine on an FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 6: 112-121 (2013) - Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013) - Katsuya Fujiwara
, Hideo Fujiwara, Hideo Tamamoto:
Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. IPSJ Trans. Syst. LSI Des. Methodol. 6: 27-33 (2013) - Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. IPSJ Trans. Syst. LSI Des. Methodol. 6: 122-126 (2013) - Kazuhito Ito, Kazuhiko Kameda:
A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. IPSJ Trans. Syst. LSI Des. Methodol. 6: 60-70 (2013) - Xin Jiang, Ran Zhang, Takahiro Watanabe:
An Efficient Algorithm for 3D NoC Architecture Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6: 34-41 (2013) - Yuta Kato, Kenshu Seto:
Loop Fusion with Outer Loop Shifting for High-level Synthesis. IPSJ Trans. Syst. LSI Des. Methodol. 6: 71-75 (2013) - Huang-Chih Kuo, Youn-Long Lin:
VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. IPSJ Trans. Syst. LSI Des. Methodol. 6: 76-93 (2013) - Yoonmyung Lee
, Dongmin Yoon, Yejoong Kim
, David T. Blaauw, Dennis Sylvester:
Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 17-26 (2013) - Kosuke Mizuno, Yosuke Terachi, Kenta Takagi
, Shintaro Izumi, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
An FPGA Implementation of a HOG-based Object Detection Processor. IPSJ Trans. Syst. LSI Des. Methodol. 6: 42-51 (2013) - Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 52-59 (2013) - Sangyoung Park, Younghyun Kim
, Jaehyun Park
, Naehyuck Chang:
Power Converter-aware Design of Electronics Systems. IPSJ Trans. Syst. LSI Des. Methodol. 6: 2-16 (2013) - Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Jörg Bormann, Markus Wedler, Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz:
A New Formal Verification Approach for Hardware-dependent Embedded System Software. IPSJ Trans. Syst. LSI Des. Methodol. 6: 135-145 (2013) - Yiqiang Sheng, Atsushi Takahashi
:
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6: 94-100 (2013) - Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga:
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6: 127-134 (2013) - Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 6: 1 (2013) - 2012
- Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
:
Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 106-117 (2012) - Hirotaka Kawashima, Gang Zeng, Hideki Takase
, Masato Edahiro, Hiroaki Takada:
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework. IPSJ Trans. Syst. LSI Des. Methodol. 5: 133-142 (2012) - Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
A Stackable LTE Chip for Cost-effective 3D Systems. IPSJ Trans. Syst. LSI Des. Methodol. 5: 2-13 (2012) - Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012) - Sungho Park, Ahmed Al-Maashri
, Kevin M. Irick, Aarti Chandrashekhar, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Vijaykrishnan Narayanan:
System-On-Chip for Biologically Inspired Vision Applications. IPSJ Trans. Syst. LSI Des. Methodol. 5: 71-95 (2012) - Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Fast Performance Estimation Framework for System-Level Design Space Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 5: 44-54 (2012) - Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012) - Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 5: 1 (2012) - Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura:
Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology. IPSJ Trans. Syst. LSI Des. Methodol. 5: 118-132 (2012) - Michitarou Yabuuchi, Kazutoshi Kobayashi:
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 143-149 (2012)