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"0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its ..."

Yohei Nakata et al. (2012)

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DOI: 10.2197/IPSJTSLDM.5.32

access: closed

type: Journal Article

metadata version: 2024-03-11

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Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012)

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