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ORCIDYuichi Nakamura 0002
Person information
- affiliation: NEC Corp., Kawasaki, Japan
- affiliation (PhD 2007): Waseda University, Graduate School of Information, Production and Systems, Japan
Other persons with the same name
- Yuichi Nakamura 0001
![[0000-0001-5103-7194]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5103-7194")
— Kyoto University, Sakyo, Japan (and 1 more) - Yuichi Nakamura 0003 — IBM Japan, Tokyo Research Laboratory, Japan (and 1 more)
- Yuichi Nakamura 0004 — SoftBank Corp. (and 2 more)
- Yuichi Nakamura 0005 — Hitachi Solutions Ltd., Japan (and 1 more)
- Yuichi Nakamura 0006 — Anan National College of Technology, Japan (and 1 more)
- Yuichi Nakamura 0007 — Toyohashi University of Technology, Japan
- Yuichi Nakamura 0008 — Yatsushiro National College of Technology, Japan
- Yuichi Nakamura 0009 — Tokai University, Department of Information Media Technology, Hiratsuka, Japan
- Yuichi Nakamura 0010 — University of Tokyo, Institute of Industrial Science, Japan
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2020 – today
- 2023
[j23]Rafael Sotelo, Jingbo Wang, Yuichi Nakamura, Ahmed Farouk, Rosario Arjona, Salvador E. Venegas-Andraca, Alex James, Araceli Venegas-Gomez, Bill Gonzalez:
The First Workshop on Quantum in Consumer Technology at IEEE Quantum Week 2022. IEEE Consumer Electron. Mag. 12(5): 10-11 (2023)- [c30]Yuichi Nakamura, Hitoshi Takeshita:
Technologies for Optical Submarine Cables: Past Present & Future. OFC 2023: 1-3 - 2021
- [c29]Yasuhiro Takashima, Yuichi Nakamura:
Theoretical and Experimental Analysis of Traveling Salesman Walk Problem. APCCAS 2021: 241-244 - [c28]Yuichi Nakamura:
Can Quantum Technologies Change "Consumer Electronics"? ICCE 2021: 1
2010 – 2019
- 2019
- [c27]Hitoshi Takeshita, Masaki Sato, Yoshihisa Inada, Emmanuel Le Taillandier de Gabory, Yuichi Nakamura:
Past, Current and Future Technologies for Optical Submarine Cables. PHOTONICS@SC 2019: 36-42 - 2018
- [j22]Jiang Xu, Yuichi Nakamura, Andrew B. Kahng:
Silicon Photonics for Computing Systems. ACM J. Emerg. Technol. Comput. Syst. 14(2): 20 (2018) - [c26]Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura:
Task Allocation and Scheduling Optimization in the Heterogeneous Core System. NGCAS 2018: 86-89 - 2017
- [j21]Linghe Kong, Kui Ren, Muhammad Khurram Khan, Qi Li, Ammar Rayes, Mérouane Debbah, Yuichi Nakamura:
Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 1. IEEE Commun. Mag. 55(3): 60-61 (2017) - [j20]Linghe Kong, Kui Ren, Muhammad Khurram Khan, Qi Li, Ammar Rayes, Mérouane Debbah, Yuichi Nakamura:
Sustainable Incentive Mechanisms for Mobile Crowdsensing: Part 2. IEEE Commun. Mag. 55(6): 118-119 (2017) - [j19]Jianquan Liu, Shoji Nishimura, Takuya Araki, Yuichi Nakamura:
A Loitering Discovery System Using Efficient Similarity Search Based on Similarity Hierarchy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 367-375 (2017) - [c25]Takuya Araki, Yuichi Nakamura:
Future trend of deep learning frameworks - From the perspective of big data analytics and HPC. APSIPA 2017: 696-703 - [c24]Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura:
Accelerating NFV application using CPU-FPGA tightly coupled architecture. FPT 2017: 136-143 - [c23]Yuichi Nakamura, Hideyuki Shimonishi, Yuki Kobayashi, Kozo Satoda, Yashuhiro Matsunaga, Dai Kanetomo:
Novel heterogeneous computing platforms and 5G communications for IoT applications. ICCAD 2017: 874-879 - [c22]Yuichi Nakamura:
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices. ISPD 2017: 113-114 - 2016
- [c21]Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura:
PEVaS: Power and execution-time variation-aware scheduling for MPSoC. NEWCAS 2016: 1-4 - [c20]Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura, Jiang Xu:
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. NOCS 2016: 1-8 - 2015
- [j18]Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi:
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2572-2583 (2015) - [c19]Takashi Takenaka, Hiroaki Inoue, Takeo Hosomi, Yuichi Nakamura:
FPGA-accelerated complex event processing. VLSIC 2015: 126- - 2014
- [c18]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - 2013
- [j17]Naoya Okada, Yuichi Nakamura, Shinji Kimura:
Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1264-1272 (2013) - [j16]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 52-59 (2013) - [c17]Shogo Nakaya, Yuichi Nakamura:
Adaptive sensing of ECG signals using R-R interval prediction. EMBC 2013: 9-12 - [c16]Masamichi Takagi, Yuichi Nakamura, Atsushi Hori, Balazs Gerofi, Yutaka Ishikawa:
Revisiting rendezvous protocols in the context of RDMA-capable host channel adapters and many-core processors. EuroMPI 2013: 85-90 - 2012
- [j15]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News 40(5): 87-92 (2012) - [c15]Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura:
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. MCSoC 2012: 100-106 - 2011
- [j14]Yuichi Nakamura:
A Verification and Analysis Tool Set for Embedded System Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2788-2793 (2011) - [c14]Wei Chen, Xiaolin Zhang, Takeshi Yoshimura, Yuichi Nakamura:
A low power technology mapping method for Adaptive Logic Module. FPT 2011: 1-5 - [c13]Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako:
Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. HOST 2011: 57-62 - 2010
- [j13]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. IPSJ Trans. Syst. LSI Des. Methodol. 3: 81-90 (2010) - [c12]Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura:
Delay analysis of sub-path on fabricated chips by several path-delay tests. ISCAS 2010: 1595-1598
2000 – 2009
- 2009
- [c11]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL 2009: 212-217 - 2008
- [j12]Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura:
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2322-2327 (2008) - [j11]Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura:
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3531-3538 (2008) - [j10]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3539-3547 (2008) - [j9]Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi:
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools. IPSJ Trans. Syst. LSI Des. Methodol. 1: 58-66 (2008) - [j8]Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura:
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition. IPSJ Trans. Syst. LSI Des. Methodol. 1: 67-77 (2008) - [c10]Yuichi Nakamura:
A design method for skew tolerant latch design. APCCAS 2008: 356-359 - [c9]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803 - 2007
- [j7]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 924-931 (2007) - [j6]Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura:
A Relocation Method for Circuit Modifications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2743-2751 (2007) - [j5]Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura:
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2810-2817 (2007) - 2006
- [j4]Yuichi Nakamura, Takeshi Yoshimura:
Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3458-3463 (2006) - [j3]Yuichi Nakamura, Kohei Hosokawa:
Fast FPGA-Emulation-Based Simulation Environment for Custom Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3464-3470 (2006) - [j2]Ko Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura:
Domino Logic Synthesis System and its Applications. J. Circuits Syst. Comput. 15(2): 277-287 (2006) - [c8]Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa:
Budgeting-free hierarchical design method for large scale and high-performance LSIs. DAC 2006: 955-958 - [c7]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT 2006: 361-364 - 2005
- [j1]Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura:
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3351-3357 (2005) - [c6]Yuichi Nakamura, Takeshi Yoshimura:
A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. ISCAS (1) 2005: 628-631 - 2004
- [c5]Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura:
Timing optimization by replacing flip-flops to latches. ASP-DAC 2004: 186-191 - [c4]Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura:
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. DAC 2004: 299-304
1990 – 1999
- 1997
- [c3]Yoshiyuki Ito, Yuichi Nakamura:
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface. ASP-DAC 1997: 377-382 - 1995
- [c2]Yuichi Nakamura, Takeshi Yoshimura:
A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix. DAC 1995: 653-657 - [c1]Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita:
Multi-Level Logic Minimization Based on Multi-Signal Implications. DAC 1995: 658-662
Coauthor Index
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