"Energy-efficient High-level Synthesis for HDR Architectures with Clock ..."

Hiroyuki Akasaka et al. (2013)

> Home

Details and statistics

DOI: 10.2197/IPSJTSLDM.6.101

access: closed

type: Journal Article

metadata version: 2020-09-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ipsj/AkasakaAYT13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ipsj/AkasakaAYT13
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.