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2020 – today
- 2024
- [c38]J. Luge-Alvarez, J. B. David, Alexandre Siligaris, Vincent Puyal, G. Moritz, Tadeu Mota Frutuoso, V. Lapras, Claire Fenouillet-Béranger, Laurent Brunet, P. Vincent, Didier Lattard, Xavier Garros, François Andrieu, Perrine Batude:
First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. VLSI Technology and Circuits 2024: 1-2 - 2021
- [j7]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021) - 2020
- [c37]Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard:
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. DATE 2020: 1740-1745 - [c36]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48 - [i1]Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu:
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR abs/2012.00061 (2020)
2010 – 2019
- 2019
- [c35]Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet:
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 3DIC 2019: 1-5 - [c34]Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné:
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC 2019: 1-4 - [c33]Pascal Vivet, Gilles Sicard, Laurent Millet, Stéphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sébastien Thuries, Didier Lattard, Séverine Cheramy, Perrine Batude, Fabien Clermidy:
Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. DATE 2019: 674-679 - [c32]Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné:
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS 2019: 1-2 - 2018
- [c31]Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet:
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - [c30]Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné:
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS 2018: 1-6 - [c29]Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude:
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS 2018: 157-160 - [c28]François Andrieu, Perrine Batude, Laurent Brunet, Claire Fenouillet-Béranger, Didier Lattard, Sébastien Thuries, Olivier Billoint, Richard Fournel, Maud Vinet:
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. ICICDT 2018: 141-144 - [c27]Lucile Arnaud, Stéphane Moreau, Amadine Jouve, Imed Jani, Didier Lattard, F. Fournel, C. Euvrard, Y. Exbrayat, Viorel Balan, Nicolas Bresson, S. Lhostis, J. Jourdon, E. Deloffre, S. Guillaumet, Alexis Farcy, Simon Gousseau, M. Arnoux:
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability. IRPS 2018: 4 - 2017
- [j6]Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel:
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits 52(1): 33-49 (2017) - [c26]Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné:
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS 2017: 153-156 - 2016
- [j5]Perceval Coudrain, Papa Momar Souare, Rafael Prieto, Vincent Fiori, Alexis Farcy, Laurent Le Pailleur, Jean-Philippe Colonna, Cristiano Santos, Pascal Vivet, M. Haykel Ben Jamaa, Denis Dutoit, François de Crecy, Sylvain Dumas, Christian Chancel, Didier Lattard, Séverine Cheramy:
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Des. Test 33(3): 21-36 (2016) - [c25]Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, Gaël Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy:
ITAC: A complete 3D integration test platform. 3DIC 2016: 1-4 - [c24]Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos:
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC 2016: 146-147 - 2015
- [c23]Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy:
3D advanced integration technology for heterogeneous systems. 3DIC 2015: FS6.1-FS6.3 - [c22]Vincent Lenoir, Didier Lattard, Ahmed Amine Jerraya:
An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs. ISCAS 2015: 1222-1225 - [c21]Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet:
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS 2015: 1550-1553 - [c20]Vincent Lenoir, Warody Lombardi, Didier Lattard, Ahmed Amine Jerraya:
Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB. NEWCAS 2015: 1-4 - 2014
- [c19]Vincent Lenoir, Didier Lattard, Francois Dehmas, Dominique Morche, Ahmed Amine Jerraya:
Non-coherent detection of M-ary orthogonal signals using Compressive Sensing. CSNDSP 2014: 923-927 - [c18]Vincent Lenoir, Didier Lattard, Francois Dehmas, Dominique Morche, Ahmed Amine Jerraya:
Computational load reduction by downsampling for energy-efficient digital baseband. NEWCAS 2014: 333-336 - 2012
- [j4]Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
A Stackable LTE Chip for Cost-effective 3D Systems. IPSJ Trans. Syst. LSI Des. Methodol. 5: 2-13 (2012) - [j3]Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip. Softw. Pract. Exp. 42(7): 877-890 (2012) - [c17]Timothé Laforest, Antoine Dupret, Arnaud Verdant, Didier Lattard, Patrick Villard:
Algorithm architecture co-design for ultra low-power image sensor. Sensors, Cameras, and Systems for Industrial and Scientific Applications 2012: 829806 - 2011
- [c16]Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
A 3D reconfigurable platform for 4G telecom applications. DATE 2011: 555-558 - 2010
- [c15]Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. DATE 2010: 184-189 - [c14]Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
Flexible and distributed real-time control on a 4G telecom MPSoC. ISCAS 2010: 3961-3964 - [c13]Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio. ISVLSI 2010: 345-350 - [c12]Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
An efficient hierarchical router for large 3D NoCs. International Symposium on Rapid System Prototyping 2010: 1-5
2000 – 2009
- 2009
- [c11]Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
High level modelling and performance evaluation of address mapping in NAND flash memory. ICECS 2009: 659-662 - 2008
- [j2]Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens:
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits 43(1): 223-235 (2008) - [c10]Carolynn Bernier, Frédéric Hameau, Gérard Billiot, Emeric de Foucauld, Stéphanie Robinet, Didier Lattard, Jean Durupt, Francois Dehmas, Laurent Ouvry, Pierre Vincent:
An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications. ESSCIRC 2008: 426-429 - [c9]Camille Jalier, Didier Lattard, Gilles Sassatelli:
A flexible modeling and simulation framework for Design Space Exploration. SoC 2008: 1-4 - 2007
- [c8]Didier Lattard:
Trends in complex SoC Design: From technology variability to multiprocessor architectures. ICECS 2007: 1 - [c7]Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens:
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC 2007: 258-601 - 2005
- [c6]Julien Delorme, Dominique Houzet, Romain Lemaire, Didier Lattard:
Proposition of a benchmark for evaluation of cores mapping onto NoC architectures. ReCoSoC 2005: 93-98 - [c5]Romain Lemaire, Fabien Clermidy, Yves Durand, Didier Lattard, Ahmed Amine Jerraya:
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. IEEE International Workshop on Rapid System Prototyping 2005: 24-30
1990 – 1999
- 1996
- [c4]Dominique Noguet, Alain Merle, Didier Lattard:
A Data Dependent Architecture Based on Seeded Region Growing Strategy for Advanced Morphological Operators. ISMM 1996: 235-243 - 1991
- [j1]Didier Lattard, Guy Mazaré:
A VLSI implementation of parallel image reconstruction. CVGIP Graph. Model. Image Process. 53(6): 581-591 (1991) - 1990
- [c3]Didier Lattard, Bernard Faure, Guy Mazaré:
Massively parallel architecture: application to neural net emulation and image reconstruction. ASAP 1990: 214-225
1980 – 1989
- 1989
- [b1]Didier Lattard:
Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction). Grenoble Institute of Technology, France, 1989 - 1988
- [c2]Didier Lattard, Guy Mazaré:
An Integrated Highly Parallel Architecture for Image Reconstruction. Advances in Computer Graphics Hardware 1988: 53-64 - [c1]Didier Lattard, Guy Mazaré:
An Integrated Asynchronous Cellular Array to Do Parallel Image Reconstruction. MVA 1988: 128-131
Coauthor Index
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