- 2009
- Abdallatif S. Abu-Issa, Steven F. Quigley:
Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 755-759 (2009) - Erkan Acar, Sule Ozev:
Low-Cost Characterization and Calibration of RF Integrated Circuits through I - Q Data Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 993-1005 (2009) - Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto:
A Transform-Parametric Approach to Boolean Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 805-817 (2009) - Nisar Ahmed, Mohammad Tehranipoor:
A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1573-1582 (2009) - Andrea Alimonda, Salvatore Carta, Andrea Acquaviva, Alessandro Pisano, Luca Benini:
A Feedback-Based Approach to DVFS in Data-Flow Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1691-1704 (2009) - Sobeeh Almukhaizim, Ozgur Sinanoglu:
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 298-302 (2009) - Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 478-489 (2009) - Behnam Amelifard, Massoud Pedram:
Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 888-900 (2009) - Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 111-120 (2009) - Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy:
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1127-1137 (2009) - Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu:
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 651-661 (2009) - Sung-Yong Bang, Kwanhu Bang, Sungroh Yoon, Eui-Young Chung:
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1334-1347 (2009) - Giovanni Beltrame, Luca Fossati, Donatella Sciuto:
ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1857-1869 (2009) - Bradley N. Bond, Luca Daniel:
Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1467-1480 (2009) - Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani:
Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear Periodic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 447-451 (2009) - Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain:
A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1613-1626 (2009) - Gianpiero Cabodi, Sergio Nocco, Stefano Quer:
Strengthening Model Checking Techniques With Inductive Invariants. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 154-158 (2009) - Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir:
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1728-1741 (2009) - Josep Carmona, Jordi Cortadella, Michael Kishinevsky, Alexander Taubin:
Elastic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1437-1455 (2009) - Rajat Subhra Chakraborty, Swarup Bhunia:
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1493-1502 (2009) - Hoseok Chang, Wonyong Sung:
Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 158-163 (2009) - Jiajia Chen, Chip-Hong Chang:
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1844-1856 (2009) - Quan Chen, Hoi Wai Choi, Ngai Wong:
Robust Simulation Methodology for Surface-Roughness Loss in Interconnect and Package Modelings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1654-1665 (2009) - Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang:
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 193-206 (2009) - Duo Chen, Dan Jiao:
Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1138-1149 (2009) - Lerong Cheng, Puneet Gupta, Lei He:
Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1777-1781 (2009) - Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 130-140 (2009) - Lih-Yih Chiou, Yi-Siou Chen, Chih-Hsien Lee:
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1213-1223 (2009) - Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek:
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 554-567 (2009) - Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan:
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1006-1016 (2009)