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2020 – today
- 2024
[j30]Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava:
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application. J. Electron. Test. 40(2): 171-184 (2024)- [c33]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems. ISCAS 2024: 1-5 - [i2]Ajinkya Shinde, Gaurav Sharma, Manisha Pattanaik, Sri Niwas Singh:
Effect of Fog Particle Size Distribution on 3D Object Detection Under Adverse Weather Conditions. CoRR abs/2408.01085 (2024) - 2023
- [j29]Anil Kumar Rajput
, Alok Kumar Tiwari, Manisha Pattanaik:
An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices. Circuits Syst. Signal Process. 42(6): 3589-3616 (2023) - [j28]Richa Sharma, G. K. Sharma, Manisha Pattanaik, V. S. S. Prashant:
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. J. Electron. Test. 39(4): 465-485 (2023) - [j27]Anil Kumar Rajput, Manisha Pattanaik:
Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. Microelectron. J. 137: 105795 (2023) - [c32]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. APCCAS 2023: 80-84 - [c31]Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal:
An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. VLSID 2023: 133-138 - 2022
- [j26]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems. J. Electron. Test. 38(6): 667-682 (2022) - [j25]Abhishek Gupta, Somesh Kumar, Manisha Pattanaik:
Coverage hole detection using social spider optimized Gaussian Mixture Model. J. King Saud Univ. Comput. Inf. Sci. 34(10 Part B): 9814-9821 (2022) - [j24]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations. Microprocess. Microsystems 90: 104498 (2022) - [j23]Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal:
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. Microelectron. J. 129: 105569 (2022) - 2021
- [j22]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency. Integr. 76: 1-12 (2021) - [j21]Richa Sharma, Vijaypal Singh Rathor, G. K. Sharma, Manisha Pattanaik:
A new hardware Trojan detection technique using deep convolutional neural network. Integr. 79: 1-11 (2021) - [j20]Neelam Arya, Manisha Pattanaik, G. K. Sharma:
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1994-1997 (2021) - [c30]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. VLSID 2021: 163-168 - 2020
- [j19]Amit Kumar, Manisha Pattanaik, Pankaj Srivastava, Kamal Kishor Jha:
Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications. IET Circuits Devices Syst. 14(3): 270-275 (2020) - [j18]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Bit significance based reconfigurable approximate restoring dividers and square rooters. Microelectron. J. 104: 104861 (2020) - [c29]Anil Kumar Rajput, Manisha Pattanaik:
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. VDAT 2020: 1-4 - [c28]Richa Sharma, Nitya Kritin Valivati, G. K. Sharma, Manisha Pattanaik:
A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. VDAT 2020: 1-6 - [c27]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. VLSID 2020: 90-95
2010 – 2019
- 2019
- [c26]Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal:
Semantic Image Completion and Enhancement using Deep Learning. ICCCNT 2019: 1-6 - [c25]Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma:
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. VDAT 2019: 398-412 - [i1]Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal:
Semantic Image Completion and Enhancement using Deep Learning. CoRR abs/1911.02222 (2019) - 2018
- [j17]Vikas Mahor, Manisha Pattanaik:
A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. Circuits Syst. Signal Process. 37(2): 475-499 (2018) - [c24]Vinay Gupta, Pratiksha Shukla, Manisha Pattanaik:
Low Leakage Noise Tolerant 10T SRAM Cell. VDAT 2018: 538-550 - [c23]Pratiksha Shukla, Vinay Gupta, Manisha Pattanaik:
Low Leakage Read Write Enhanced 9T SRAM Cell. VDAT 2018: 565-577 - 2017
- [j16]Vikas Mahor, Manisha Pattanaik:
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. Circuits Syst. Signal Process. 36(12): 4789-4808 (2017) - [c22]Amit Singh Rajput, Manisha Pattanaik, Ritesh Kumar Tiwari:
Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology. iNIS 2017: 234-237 - 2016
- [j15]Vijay Kumar Sharma, Manisha Pattanaik:
Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library. J. Circuits Syst. Comput. 25(11): 1650134:1-1650134:16 (2016) - [c21]Vivek Kumar, Vikas Mahor, Manisha Pattanaik:
Novel Ultra Low Leakage FinFET Based SRAM Cell. iNIS 2016: 89-92 - [c20]Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik:
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. iNIS 2016: 268-273 - [c19]Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik:
FinFET-Based Low Power Address Decoder under Process Variation. iNIS 2016: 274-277 - 2015
- [j14]Vikas Mahor, Manisha Pattanaik:
Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. J. Circuits Syst. Comput. 24(5): 1550073:1-1550073:20 (2015) - [j13]Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma:
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. J. Low Power Electron. 11(1): 49-62 (2015) - [j12]Vikas Mahor, Manisha Pattanaik:
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. J. Low Power Electron. 11(2): 225-235 (2015) - [j11]Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma:
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Microelectron. Reliab. 55(8): 1131-1143 (2015) - [c18]Rohit Kumar, Manisha Pattanaik:
A novel dual multiplier floating point multiply accumulate architecture. VDAT 2015: 1-2 - [c17]Gagan Deep Verma, Manisha Pattanaik:
Performance study of side block oxide band gap engineered SONOS: A device simulation approach. VDAT 2015: 1-4 - 2014
- [j10]Vijay Kumar Sharma, Manisha Pattanaik:
Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study. J. Circuits Syst. Comput. 23(5) (2014) - [j9]Vijay Kumar Sharma, Manisha Pattanaik:
Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits. J. Low Power Electron. 10(1): 45-52 (2014) - [j8]Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik:
Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. Microelectron. J. 45(11): 1515-1521 (2014) - [j7]Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj:
PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron. Reliab. 54(1): 90-99 (2014) - [j6]Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik:
Edge preservation of impulse noise filtered images by improved anisotropic diffusion. Multim. Tools Appl. 73(1): 573-597 (2014) - [j5]Vijay Kumar Sharma, Sumit Patel, Manisha Pattanaik:
High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell. Wirel. Pers. Commun. 78(1): 57-68 (2014) - [c16]Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma:
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. NANOARCH 2014: 122-128 - [c15]Shipra Bassi, Manisha Pattanaik:
TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach. VDAT 2014: 1-6 - [c14]Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma:
Operation-aware assist circuit design for improved write performance of FinFET based SRAM. VDAT 2014: 1-6 - 2013
- [j4]Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik:
Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement. Signal Process. 93(6): 1684-1693 (2013) - [c13]Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik, G. K. Sharma:
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. ECCTD 2013: 1-4 - 2012
- [c12]Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik:
Fuzzy based diffusion coefficient function in anisotropic diffusion for impulse noise removal. ICVGIP 2012: 67 - [c11]Santhosh Keshavarapu, Saumya Jain, Manisha Pattanaik:
A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell. ISED 2012: 97-101 - [c10]Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik:
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. ISED 2012: 151-153 - [c9]Shashikant Sharma, Manisha Pattanaik, Balwinder Raj:
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. ISED 2012: 272-275 - 2011
- [j3]Shilpi Birla, Rakesh Kumar Singh, Manisha Pattanaik:
Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications. Circuits Syst. 2(4): 274-280 (2011) - [j2]Shilpi Birla, Neeraj Kumar Shukla, Kapil Rathi, Rakesh Kumar Singh, Manisha Pattanaik:
Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology. Circuits Syst. 2(4): 326-329 (2011) - [j1]Subhra Dhar, Manisha Pattanaik, Poolla Rajaram:
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. VLSI Design 2011: 178516:1-178516:19 (2011) - [c8]Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor:
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED 2011: 118-123 - [c7]Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik:
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. ISVLSI 2011: 49-53 - [c6]Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik:
A New Adaptive Thresholding in SVD for Efficient Image De-noising. SocProS (2) 2011: 659-670 - 2010
- [c5]Deepak Kumar, Pankaj Kumar, Manisha Pattanaik:
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. DSD 2010: 404-407 - [c4]Nishant Khanwalkar, Shashikala Tapaswi, Manisha Pattanaik:
An Efficient Compressed Domain Spatial Transcoding Scheme for Adaptive Video Content Delivery. PCM (2) 2010: 245-251 - [c3]Deepak Kumar, Pankaj Kumar, Manisha Pattanaik:
Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design. SBCCI 2010: 2-7 - [c2]Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik:
An efficient image noise removal and enhancement method. SMC 2010: 3735-3740
2000 – 2009
- 2003
- [c1]Manisha Pattanaik, Swapna Banerjee:
A New Approach to Analyze a Sub-micron CMOS Inverter. VLSI Design 2003: 116-121
Coauthor Index
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last updated on 2024-10-07 22:24 CEST by the dblp team
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