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ORCIDISED 2011: Kochi, Kerala, India
- International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1880-9
- Zubair Akhter
, Nagendra Prasad Pathak:
Concurrent Dual Band Transmitter for 2.4/5.2GHz Wireless LAN Applications. 1-5 - Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra:
Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL. 6-11 - Shravan Kudikala, Samrat L. Sabat, Siba K. Udgata:
Performance Study of Harmony Search Algorithm for Analog Circuit Sizing. 12-17 - Hirak Patangia, Sri Nikhil Gupta Gourisetti:
A Harmonically Superior Switching Modulator with Wide Baseband and Real-Time Tunability. 18-23 - Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. 24-29 - Manoj Kumar Meena, Rohit Khanna, Dipankar:
Nonlinear Inductance Measurement Using an Energy Storage Approach. 30-33 - Sandeep Goud Surya, Sudip Nag, Avil J. Fernandes, Sahir Gandhi, Dilip Agarwal, Gaurav Chatterjee, V. Ramgopal Rao:
Highly Sensitive ?R/R Measurement System for Nano-electro-Mechanical Cantilever Based Bio-sensors. 34-38 - Saraju P. Mohanty, Elias Kougianos:
PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression. 39-44 - Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan:
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. 45-50 - Bimal Kumar Meher, Pramod Kumar Meher:
A New Look-Up Table Approach for High-Speed Finite Field Multiplication. 51-55 - T. C. Lad, Anand D. Darji, S. N. Merchant, Arun N. Chandorkar:
VLSI Implementation of Wavelet Based Robust Image Watermarking Chip. 56-61 - K. Srinivasa Reddy, M. S. Bharath, S. K. Sahoo, S. Sinha, J. P. Reddy:
Design of Low Power, High Performance FIR Filter Using Modified Differential Evolution Algorithm. 62-66 - Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat:
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. 67-71 - Naveen Sudhish, Raghavendra BR, Harish Yagain:
An Efficient Method for Using Transaction Level Assertions in a Class Based Verification Environment. 72-76 - V. Rakesh, Kavallur Gopi Smitha, A. Prasad Vinod:
Low Complexity Flexible Hardware Efficient Decimation Selector. 77-81 - Suresh Kumar Varanasi, Satyam Mandavilli:
Process Variation Tolerant SRAM Cell Design. 82-87 - Manish M. Patil, Shaila Subbaraman, Shirish Joshi:
Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC Systems. 88-93 - Manish Baphna, Anchal Jain, Ashish Mathur:
A Method to Reuse RTL Verification Tests to Validate Cycle Accurate Model. 94-99 - Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. 100-105 - S. Srinivasan, V. Kamakoti, A. Bhattacharya:
Towards Quick Solutions for Generalized Placement Problem. 106-111 - Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
Single-Event Transient Analysis in High Speed Circuits. 112-117 - Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor:
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. 118-123 - Ramracksha Tripathi, Shivshankar Mishra, S. G. Prakash:
A Novel 14-Transistors Low-Power High-Speed PPM Adder. 124-128 - Ashok Kumar Suhag, Vivek Shrivastava:
Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage. 129-133 - K. Sajeesh, Hemangee K. Kapoor:
An Authenticated Encryption Based Security Framework for NoC Architectures. 134-139 - Ramkumar Jayaraman, Handi Kartadihardja, Douglas L. Maskell:
Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications. 140-145 - Nachiketa Das, Pranab Roy, Hafizur Rahaman:
Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application. 146-151 - Wei Jhih Wang, Chang Hong Lin:
An Improved BitMask Based Code Compression Algorithm for Embedded Systems. 152-157 - Harish Yagain, Srinivas Donapati:
Addressing the Interoperability Issues While Using JPEG-XR. 158-163 - Pratibha Sawhney, G. Ganesh, A. K. Bhattacharjee:
Automatic Construction of Runtime Monitors for FPGA Based Designs. 164-169 - Karthik K. P., P. Rangababu, Samrat L. Sabat, Jagannath Nayak:
System on Chip Implementation of Adaptive Moving Average Based Multiple-Model Kalman Filter for Denoising Fiber Optic Gyroscope Signal. 170-175 - Pranab Roy, Hafizur Rahaman, Rupam Bhattacharya, Parthasarathi Dasgupta:
A Best Path Selection Based Parallel Router for DMFBs. 176-181 - Debaprasad Das, Hafizur Rahaman:
Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon Interconnects. 182-187 - Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman:
Optimization of Test Wrapper for TSV Based 3D SOCs. 188-193 - Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. 194-199 - Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. 200-205 - Narayanan M. Komerath, Aravinda Kar, Rajkumar Pant:
Antenna Considerations for Retail Beamed Power Delivery in India. 206-211 - Amrita Som, Amlan Chakrabarti:
A New BSQDD Approach for Synthesis of Quantum Circuit. 212-216 - Yalcin Yilmaz, Pinaki Mazumder:
Threshold Read Method for Multi-bit Memristive Crossbar Memory. 217-222 - Indrajit Pan, Parthasarathi Dasgupta, Hafizur Rahaman, Tuhina Samanta:
Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip. 223-229 - Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman:
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. 230-235 - Bibhash Sen, Divyam Saran, Mousumi Saha, Biplab K. Sikdar:
Synthesis of Reversible Universal Logic around QCA with Online Testability. 236-241 - Rajkumar Pant, Narayanan M. Komerath, Aravinda Kar:
Application of Lighter-Than-Air Platforms for Power Beaming, Generation and Communications. 242-247 - Satyajeet Nimgaonkar, Mahadevan Gomathisankaran:
Energy Efficient Memory Authentication Mechanism in Embedded Systems. 248-253 - Aminul Islam, Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan:
Low Active Power High Speed Cache Design. 254-259 - B. Chitti Babu, Sriharsha, M. V. Ashwin Kumar, Nikhil Saroagi, S. R. Samantaray:
Design and Implementation of Low Power Smart PV Energy System for Portable Applications Using Synchronous Buck Converter. 260-266 - Mamatha Samson, Satyam Mandavalli:
Adiabatic 5T SRAM. 267-272 - Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul:
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. 273-278 - Himesh Joshi, Maryam Shojaei Baghini:
Versatile Battery Chargers for New Age Batteries. 279-284 - S. D. Pable, Mohd. Hasan, Mohd. Ajmal Kafeel:
Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology. 285-289 - Jayashree Vaddin, Shaila Subbaraman:
DCSFPSS Assisted Morphological Approach for Grey Twill Fabric Defect Detection and Defect Area Measurement for Fabric Grading. 290-295 - Vishram Mishra, Chiew Tong Lau, Syin Chan, Jimson Mathew:
MAC Protocol for Two Level QoS Support in Cognitive Radio Network. 296-301 - J. K. Mandal, Somnath Mukhopadhyay:
A Novel Variable Mask Median Filter for Removal of Random Valued Impulses in Digital Images (VMM). 302-306 - Nayan V. Mujadiya:
Instruction Scheduling on Variable Latency Functional Units of VLIW Processors. 307-312 - Uttam Kr. Mondal, J. K. Mandal:
A Message Embedded Authentication of Songs to Verify Intellectual Property Right (MEAS). 313-317 - Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi:
Low-Cost Software-Implemented Error Detection Technique. 318-323 - Madhumita Sengupta, J. K. Mandal:
Image Authentication Using Hough Transform Generated Self Signature in DCT Based Frequency Domain (IAHTSSDCT). 324-328 - J. K. Mandal, Subhankar Ghatak:
A Novel Technique for Secret Communication through Optimal Shares Using Visual Cryptography (SCOSVC). 329-334 - George Rosario Dhinesh, George Rosario Jagadeesh, Thambipillai Srikanthan:
A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained Devices. 335-340 - Parthajit Roy, J. K. Mandal:
A Novel Fuzzy-GIS Model Based on Delaunay Triangulation to Forecast Facility Locations (FGISFFL). 341-346 - J. K. Mandal, Amrita Khamrui:
A Data-Hiding Scheme for Digital Image Using Pixel Value Differencing (DHPVD). 347-351 - Toshanlal Meenpal, Anup K. Bhattacharjee:
High Capacity Reversible Data Hiding Using IWT. 352-357
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