![](https://dblp1.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp1.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp1.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
default search action
Anzhela Yu. Matrosova
Person information
- affiliation: Tomsk State University, Tomsk, Russia
Refine list
![note](https://dblp1.uni-trier.de/img/note-mark.dark.12x12.png)
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
Journal Articles
- 2021
- [j5]Anzhela Yu. Matrosova, Semen Chernyshov, O. Kh. Kim, Ekaterina Nikolaeva:
Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits. Autom. Remote. Control. 82(11): 1949-1965 (2021) - 2018
- [j4]Toral Shah
, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh:
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34(1): 53-65 (2018) - 2015
- [j3]Anzhela Yu. Matrosova, Valeriy B. Lipskii:
Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits. Autom. Remote. Control. 76(4): 658-667 (2015) - 2013
- [j2]Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh:
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. 74(7): 1164-1177 (2013) - 2000
- [j1]Anzhela Yu. Matrosova, Ilya Levin
, Sergey Ostanin:
Self-checking Synchronous FSM Network Design with Low Overhead. VLSI Design 11(1): 47-58 (2000)
Conference and Workshop Papers
- 2022
- [c46]Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva
, Anzhela Yu. Matrosova
:
Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits. ISVLSI 2022: 80-85 - 2021
- [c45]Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy:
SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs. EWDTS 2021: 1-4 - [c44]Anzhela Yu. Matrosova, V. Provkin:
Applying Incompletely Specified Boolean Functions for Patch Circuit Generation. EWDTS 2021: 1-4 - 2020
- [c43]Anzhela Yu. Matrosova, V. Provkin:
Masking Internal Node Logical Faults and Trojan Circuits Injections with Using SAT Solvers. AQTR 2020: 1-4 - 2019
- [c42]Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy:
Deriving Low Power Test Sequences Detecting Robust Testable PDFs. EWDTS 2019: 1-4 - [c41]Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov:
Masking Robust Testable PDFs. EWDTS 2019: 1-4 - [c40]Anzhela Yu. Matrosova, V. Provkin, Ekaterina Nikolaeva:
Masking Internal Node Faults and Trojan Circuits in Logical Circuits. EWDTS 2019: 1-4 - 2018
- [c39]Anzhela Yu. Matrosova, Sergey Ostanin:
Trojan circuits masking and debugging of combinational circuits with LUT insertion. AQTR 2018: 1-6 - [c38]Anjela Yu. Matrosova, Semen Chernyshov, Gennadiy Goshin
, Dmitry Kudin:
Forming Patch Functions and Combinational Circuit Rectification. EWDTS 2018: 1-5 - [c37]Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov:
Finding False Paths for Sequential Circuits Using Operations on ROBDDs. IOLTS 2018: 240-242 - 2017
- [c36]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko:
Preventing and masking Trojan circuits triggering out of working area. ECCTD 2017: 1-4 - [c35]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergey Ostanin, Ekaterina Nikolaeva:
Detection and masking of Trojan Circuits in sequential logic. EWDTS 2017: 1-4 - [c34]Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina:
Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS 2017: 1-4 - [c33]Toral Shah, Anzhela Yu. Matrosova, Virendra Singh:
Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS 2017: 211-212 - [c32]Anjela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko:
Trojan circuits preventing and masking in sequential circuits. IOLTS 2017: 213-214 - [c31]Toral Shah
, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh:
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS 2017: 1-6 - 2016
- [c30]Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva
:
Patching circuit design based on reserved CLBs. AQTR 2016: 1-5 - [c29]Anzhela Yu. Matrosova, Valentina Andreeva
, Alexey Melnikov:
ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. EWDTS 2016: 1-4 - [c28]Anzhela Yu. Matrosova, Eugeniy Mitrofanov:
Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults. EWDTS 2016: 1-4 - [c27]Sergey Ostanin, Anzhela Yu. Matrosova, Natalia Butorina, V. Lavrov:
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit. EWDTS 2016: 1-4 - [c26]Toral Shah
, Virendra Singh, Anzhela Yu. Matrosova:
ROBDD based path delay fault testable combinational circuit synthesis. EWDTS 2016: 1-4 - [c25]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva:
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. IOLTS 2016: 5-6 - [c24]Satyadev Ahlawat
, Jaynarayan T. Tudu
, Anzhela Yu. Matrosova, Virendra Singh:
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS 2016: 233-238 - 2015
- [c23]Satyadev Ahlawat
, Jaynarayan T. Tudu
, Anzhela Yu. Matrosova, Virendra Singh:
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS 2015: 25-30 - [c22]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko:
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. DDECS 2015: 267-270 - [c21]Anzhela Yu. Matrosova, Valentina Andreeva
, V. Tomkov:
Fully delay and multiple stuck-at faults testable FSM design. EWDTS 2015: 1-4 - [c20]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah:
Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits. EWDTS 2015: 1-4 - [c19]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva:
Fault-tolerant high performance scheme design. EWDTS 2015: 1-4 - [c18]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah:
Simplification of fully delay testable combinational circuits. IOLTS 2015: 44-45 - [c17]Toral Shah
, Anzhela Yu. Matrosova, Virendra Singh:
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT 2015: 1-2 - 2014
- [c16]Anzhela Yu. Matrosova, Dmitry Kudin, Ekaterina Nikolaeva:
Combinational circuits without false paths. EWDTS 2014: 1-6 - [c15]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Elena Roumjantseva:
Combinational part structure simplification of fully delay testable sequential circuit. EWDTS 2014: 1-5 - [c14]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh:
Partially programmable circuit design. EWDTS 2014: 1-4 - 2013
- [c13]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Virendra Singh:
Delay testable sequential circuit designs. EWDTS 2013: 1-4 - [c12]Anzhela Yu. Matrosova, Ekaterina Nikolaeva, Dmitry Kudin, Virendra Singh:
PDF testability of the circuits derived by special covering ROBDDs with gates. EWDTS 2013: 1-5 - [c11]Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh:
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS 2013: 1-6 - 2011
- [c10]Anzhela Yu. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh:
Selection of the state variables for partial enhanced scan techniques. EWDTS 2011: 285-290 - 2010
- [c9]Anjela Yu. Matrosova, Ekaterina Nikolaeva:
PDFs testing of combinational circuits based on covering ROBDDs. EWDTS 2010: 160-163 - [c8]Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh:
Path delay faults and ENF. EWDTS 2010: 164-167 - [c7]K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur:
Fault grading using Instruction-Execution graph. EWDTS 2010: 350-357 - 2007
- [c6]Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva:
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. DFT 2007: 206-214 - 2003
- [c5]Anzhela Yu. Matrosova, Vladimir Ostrovsky, Ilya Levin
, K. Nikitin:
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. IOLTS 2003: 49-53 - 2002
- [c4]Anzhela Yu. Matrosova, Valentina Andreeva
, Yu. Sedov:
Survivable Discrete Circuits Design. IOLTW 2002: 13- - 2001
- [c3]Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin
:
Survivable Self-Checking Sequential Circuits. DFT 2001: 395-402 - [c2]Anzhela Yu. Matrosova, K. Nikitin, Olga Goloubeva:
Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation. IOLTW 2001: 144 - 2000
- [c1]Anzhela Yu. Matrosova, Sergey Ostanin:
Self-Checking FSM Design with Observing only FSM Outputs. IOLTW 2000: 153-154
Coauthor Index
![](https://dblp1.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 23:11 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint