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ORCIDJohn M. Wilson 0002
- > Home > Persons > John M. Wilson 0002
Publications
- 2024
[j9]Yoshinori Nishi
, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59(4): 1146-1157 (2024)- 2023
- [j8]Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58(4): 1062-1073 (2023) - [c19]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c18]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits 2022: 154-155 - 2020
- [c17]Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC 2020: 126-128 - 2019
- [j7]John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54(1): 43-54 (2019) - [c16]Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - 2018
- [c15]Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray:
A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. CICC 2018: 1-4 - [c14]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c13]John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC 2018: 276-278 - [c12]William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison:
Hardware-Enabled Artificial Intelligence. VLSI Circuits 2018: 3-6 - 2017
- [c11]Laura Fick, Dennis Sylvester, John W. Poulton, John M. Wilson, C. Thomas Gray:
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. ISCAS 2017: 1-4 - 2016
- [c9]John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC 2016: 156-157 - 2013
- [j6]John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray:
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. IEEE J. Solid State Circuits 48(12): 3206-3218 (2013)
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