default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDKai-Yuan Chao
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[c32]Yu Zhang
, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168- 2023
- [c31]Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. ICCAD 2023: 1-9 - 2022
- [j10]Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang:
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1957-1970 (2022) - [c30]Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho:
Multi-Package Co-Design for Chiplet Integration. ICCAD 2022: 114:1-114:9
2010 – 2019
- 2017
- [c29]Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. ASP-DAC 2017: 456-462 - 2014
- [c28]Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI 2014: 129-134 - 2013
- [j9]Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 709-722 (2013) - [c27]Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao:
Symmetrical buffered clock-tree synthesis with supply-voltage alignment. ASP-DAC 2013: 447-452 - 2012
- [j8]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 322-332 (2012) - [c26]Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC 2012: 707-712 - [c25]Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held:
Scaling the "Memory Wall": Designer track. ICCAD 2012: 271-272 - 2011
- [c24]Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638 - [c23]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC 2011: 787-792 - [c22]Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao:
High-quality global routing for multiple dynamic supply voltage designs. ICCAD 2011: 263-269 - [c21]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Lithography-aware layout modification considering performance impact. ISQED 2011: 437-441 - 2010
- [j7]Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 318-323 (2010) - [c20]Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao:
Configurable multi-product floorplanning. ASP-DAC 2010: 549-554 - [c19]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
On process-aware 1-D standard cell design. ASP-DAC 2010: 838-842 - [c18]Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing. DAC 2010: 200-205
2000 – 2009
- 2009
- [c17]Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao:
Spare-cell-aware multilevel analytical placement. DAC 2009: 430-435 - [c16]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
Wire shaping is practical. ISPD 2009: 131-138 - 2008
- [j6]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 621-632 (2008) - [j5]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 633-642 (2008) - [j4]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2197-2208 (2008) - [c15]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion. ISPD 2008: 111-117 - 2007
- [c14]Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18 - [c13]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10 - [c12]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26 - 2006
- [j3]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1754-1762 (2006) - [c11]Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration. ICCAD 2006: 633-640 - 2005
- [c10]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186 - 2004
- [j2]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 694-703 (2004) - [c9]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46 - 2003
- [c8]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434 - 2002
- [c7]Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE 2002: 690-695 - [c6]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74
1990 – 1999
- 1998
- [j1]Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 7(1): 73-84 (1998) - 1995
- [c5]Kai-Yuan Chao, D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725 - [c4]Kai-Yuan Chao, D. F. Wong:
Thermal placement for high-performance multichip modules. ICCD 1995: 218-223 - [c3]Kai-Yuan Chao, D. F. Wong:
Floorplanning for Low Power Designs. ISCAS 1995: 45-48 - [c2]Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS 1995: 207-210 - 1994
- [c1]Kai-Yuan Chao, D. F. Wong:
Layer assignment for high-performance multi-chip modules. ICCAD 1994: 680-685
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-04 21:04 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
