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2020 – today
- 2023
[c5]Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama:
A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. A-SSCC 2023: 1-3
2010 – 2019
- 2014
- [c4]Kenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai:
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. A-SSCC 2014: 29-32 - [c3]Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda
, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki:
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. ISSCC 2014: 330-331 - 2012
- [c2]Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori:
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. ISSCC 2012: 222-223
2000 – 2009
- 2005
- [j1]Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, Hubert Siedhoff:
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. IEEE J. Solid State Circuits 40(3): 736-743 (2005) - 2003
- [c1]Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama:
A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. CICC 2003: 73-76
Coauthor Index
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