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Publication search results
found 43 matches
- 2001
- Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
, Davide Sarta:
An Instruction-Level Power Analysis Model with Data Dependency. VLSI Design 12(2): 245-273 (2001) - Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou:
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 12(3): 431-448 (2001) - V. A. Bartlett, Eckhard Grass:
Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic. VLSI Design 12(3): 349-363 (2001) - Anshuman Chandra, Krishnendu Chakrabarty
, Mark C. Hansen:
Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters. VLSI Design 12(4): 475-486 (2001) - Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das:
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 12(4): 537-549 (2001) - Edward Y. C. Cheng, Sartaj K. Sahni:
A Fast Algorithm for Transistor Folding. VLSI Design 12(1): 53-60 (2001) - Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy:
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. VLSI Design 12(2): 233-243 (2001) - Jun-Dong Cho:
Preface. VLSI Design 12(2) (2001) - Jun-Dong Cho
:
Preface. VLSI Design 12(3) (2001) - Jun Dong Cho
, Jin Youn Cho:
Deep-submicron Placement Minimizing Crosstalk. VLSI Design 12(1): 1-12 (2001) - Koon-Shik Cho, Jun-Dong Cho
:
Low Power Digital Multimedia Telecommunication Designs. VLSI Design 12(3): 301-315 (2001) - Geun Rae Cho, Tom Chen:
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design 12(3): 399-406 (2001) - Jung Yun Choi, Young Hwan Kim, Kyoung-Rok Cho:
Backward Propagated Capacitance Model for Register Transfer Level Power Estimation. VLSI Design 12(2): 221-231 (2001) - Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari:
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms. VLSI Design 12(2): 101-111 (2001) - Sunil R. Das:
Guest Editorial. VLSI Design 12(4) (2001) - Alvar Dean, David Garrett, Mircea R. Stan
, Sebastian Ventrone:
Low Power Design for ASIC Cores. VLSI Design 12(3): 317-331 (2001) - John Marty Emmert, Dinesh K. Bhatia
:
Two-dimensional Placement Using Tabu Search. VLSI Design 12(1): 13-23 (2001) - G. Esakkimuthu, Hyun Suk Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations. VLSI Design 12(2): 151-165 (2001) - Taras I. Golota, Sotirios G. Ziavras:
A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers. VLSI Design 12(1): 25-52 (2001) - Shih-Chang Hsia, Chien-Cheng Tseng:
A Size-optimization Design for Variable Length Coding Using Distributed Logic. VLSI Design 12(1): 61-68 (2001) - Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das:
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design 12(4): 457-474 (2001) - Jun-Mo Jung, Jong-Wha Chong:
A Low Power FIR Filter Design for Image Processing. VLSI Design 12(3): 391-397 (2001) - Martin Kuhlmann, Keshab K. Parhi
:
A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm. VLSI Design 12(3): 365-376 (2001) - Parag K. Lala, Alvernon Walker:
A Fine Grain Configurable Logic Block for Self-checking FPGAs. VLSI Design 12(4): 527-536 (2001) - Yongha Lee, Jongho Choi, Gyu Moon, Jeomkeun Kim:
Simultaneous Switching Noise Minimization Technique Using Dual Layer Power Line Mutual Inductors. VLSI Design 12(3): 449-455 (2001) - Miriam E. Leeser
, Valerie Ohm:
Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods. VLSI Design 12(2): 187-203 (2001) - Mike J. G. Lewis, Linda E. M. Brackenbury:
CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones. VLSI Design 12(3): 333-348 (2001) - Rong Lin:
A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. VLSI Design 12(3): 377-390 (2001) - Xiaomei Liu, Prachi Sathe, Samiha Mourad:
Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates. VLSI Design 12(4): 501-513 (2001) - Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh:
Power Optimization of Delay Constrained Circuits. VLSI Design 12(2): 125-138 (2001)
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