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"A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic ..."

Rong Lin (2001)

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DOI: 10.1155/2001/97598

access: open

type: Journal Article

metadata version: 2023-05-08

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Rong Lin:
A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. VLSI Design 12(3): 377-390 (2001)

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