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Publication search results
found 52 matches
- 2008
- Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(1-3): 1 (2008) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(4): 321 (2008) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(5): 421 (2008) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(6): 505-506 (2008) - Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24(4): 353-364 (2008) - Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. 24(6): 577-590 (2008) - Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante:
Software and Hardware Techniques for SEU Detection in IP Processors. J. Electron. Test. 24(1-3): 35-44 (2008) - Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang:
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J. Electron. Test. 24(1-3): 181-192 (2008) - Myungsu Choi, Minsu Choi:
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design. J. Electron. Test. 24(1-3): 313-320 (2008) - Kyriakos Christou, Maria K. Michael, Spyros Tragoudas:
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. J. Electron. Test. 24(1-3): 203-222 (2008) - Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Performance-Optimized Design for Parametric Reliability. J. Electron. Test. 24(1-3): 129-141 (2008) - Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization. J. Electron. Test. 24(5): 481-496 (2008) - Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson:
Online Testing of MEMS Based on Encoded Stimulus Superposition. J. Electron. Test. 24(6): 555-566 (2008) - Lei Fang, Michael S. Hsiao:
Bilateral Testing of Nano-scale Fault-Tolerant Circuits. J. Electron. Test. 24(1-3): 285-296 (2008) - Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi:
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. J. Electron. Test. 24(1-3): 21-33 (2008) - Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu:
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding. J. Electron. Test. 24(1-3): 67-81 (2008) - Roberto Gómez, Alejandro Girón, Víctor H. Champac:
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J. Electron. Test. 24(6): 529-538 (2008) - Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang:
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. J. Electron. Test. 24(1-3): 57-65 (2008) - Shalabh Goyal, Abhijit Chatterjee:
Linearity Testing of A/D Converters Using Selective Code Measurement. J. Electron. Test. 24(6): 567-576 (2008) - Kristian Granhaug, Snorre Aunet:
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J. Electron. Test. 24(1-3): 157-163 (2008) - Mariagrazia Graziano, Massimo Ruo Roch:
An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS. J. Electron. Test. 24(6): 539-553 (2008) - Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. J. Electron. Test. 24(1-3): 247-257 (2008) - Guangyu Huang, Cher Ming Tan:
Reverse Breakdown Voltage Measurement for Power P+NN+ Rectifier. J. Electron. Test. 24(5): 473-479 (2008) - Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi:
Monomer Control for Error Tolerance in DNA Self-Assembly. J. Electron. Test. 24(1-3): 271-284 (2008) - Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electron. Test. 24(1-3): 259-269 (2008) - Hong-Sik Kim, Sungho Kang, Michael S. Hsiao:
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. J. Electron. Test. 24(4): 365-378 (2008) - Ho Fai Ko, Nicola Nicolici:
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24(4): 393-403 (2008) - Erik Larsson, Zebo Peng:
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. J. Electron. Test. 24(5): 497-504 (2008) - Xijiang Lin, Yu Huang:
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electron. Test. 24(4): 327-334 (2008) - Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar:
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs. J. Electron. Test. 24(1-3): 165-179 (2008)
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