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Publication search results
found 92 matches
- 2010
- Filip Adamec, Tomas Fryza:
Design - Time configurable processor basic structure. DDECS 2010: 119-120 - Liviu Agnola, Mircea Vladutiu, Mihai Udrescu:
Self-Adaptive mechanism for cache memory reliability improvement. DDECS 2010: 117-118 - Arash Ahmadpour:
A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technology. DDECS 2010: 301-304 - Davide Appello:
Safety features of SoCs: How can they be re-used? DDECS 2010: 2 - Sebastian Arming, Roman Fenkhuber, Thomas Handl:
Data compression in hardware - The Burrows-Wheeler approach. DDECS 2010: 60-65 - Snorre Aunet, Amir Hasanbegovic:
Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS. DDECS 2010: 267-272 - Mehmood-ur-Rehman Awan, Peter Koch:
Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers. DDECS 2010: 153-156 - Ali Azarpeyvand, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, Sied Mehdi Fakhraie:
Instruction reliability analysis for embedded processors. DDECS 2010: 20-23 - Yngvar Berg:
Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors. DDECS 2010: 93-98 - Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone:
Cumulative embedded memory failure bitmap display & analysis. DDECS 2010: 255-260 - Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong:
Design of a single layer programmable Structured ASIC library. DDECS 2010: 32-35 - Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang:
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288 - Martin Danek, Leos Kafka, Lukas Kohout, Jaroslav Sykora:
Instruction set extensions for multi-threading in LEON3. DDECS 2010: 237-242 - Milos Davidovic, Gerald Zach, Horst Zimmermann:
A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumption. DDECS 2010: 399-402 - Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Build-In Self-Test technique for RF Mixers. DDECS 2010: 88-92 - Roland Dobai, Elena Gramatová:
Test pattern generation for the combinational representation of asynchronous circuits. DDECS 2010: 323-328 - Rolf Drechsler, Görschwin Fey:
Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4 - Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen:
Partitioning methods for unicast/multicast traffic in 3D NoC architecture. DDECS 2010: 127-132 - Reinhard Enne, Horst Zimmermann:
An integrated low power buck converter with a comparator controlled low-side switch. DDECS 2010: 84-87 - Stefan Erb, Wolfgang Pribyl:
Comparison of jitter decomposition methods for BER analysis of high-speed serial links. DDECS 2010: 370-375 - Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina:
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS 2010: 346-351 - Stefan Frehse, Görschwin Fey, Rolf Drechsler:
A better-than-worst-case robustness measure. DDECS 2010: 78-83 - Werner Friesenbichler, Thomas Panhofer, Andreas Steininger:
A deterministic approach for hardware fault injection in asynchronous QDI logic. DDECS 2010: 317-322 - Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto:
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. DDECS 2010: 193-196 - Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS 2010: 201-204 - Ad J. van de Goor, Said Hamdioui, Georgi Gaydadjiev:
Using a CISC microcontroller to test embedded memories. DDECS 2010: 261-266 - Ad J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev:
Low-cost, customized and flexible SRAM MBIST engine. DDECS 2010: 382-387 - Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz:
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. DDECS 2010: 213-216 - Dominique Gückel, Bastian Schlich, Jörg Brauer, Stefan Kowalewski:
Synthesizing simulators for model checking microcontroller binary code. DDECS 2010: 313-316 - Jiri Halak, Sven Ubik, Petr Zejdl:
Receiver synchronization in video streaming with short latency over asynchronous networks. DDECS 2010: 403-405
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