- Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan:
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. VLSID 2016: 601-602 - Pallavi Das, Jitendra Yadav, Sujay Deb:
Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling. VLSID 2016: 591-592 - Satyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi:
Applying River Formation Dynamics to Analyze VLSI Power Grid Networks. VLSID 2016: 258-263 - Kausik Datta, Goutam Kumar Bhaumik, Rohit Goel:
An Introduction to VHDL 2008. VLSID 2016: 26-27 - Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa:
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. VLSID 2016: 439-444 - Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. VLSID 2016: 463-468 - Rolf Drechsler, Jannis Stoppe:
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC. VLSID 2016: 44-49 - Sunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi:
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications. VLSID 2016: 134-139 - Nikil D. Dutt, Nima Taherinejad:
Self-Awareness in Cyber-Physical Systems. VLSID 2016: 5-6 - Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti:
SHAKTI Processors: An Open-Source Hardware Initiative. VLSID 2016: 7-8 - Lokesh Garg, Vineet Sahula:
Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits. VLSID 2016: 252-257 - Anil Kumar Gundu, Mohammad S. Hashmi, Anuj Grover:
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications. VLSID 2016: 185-190 - Rajat Gupta, Vijit Gadi, H. Anirudh Upendar:
Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique. VLSID 2016: 318-322 - Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao:
A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package. VLSID 2016: 156-161 - Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu:
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. VLSID 2016: 445-450 - Tsung-Yi Ho, Shigeru Yamashita, Ansuman Banerjee, Sudip Roy:
Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences. VLSID 2016: 59-62 - Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan:
Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices. VLSID 2016: 264-269 - Vinayaka Jyothi, Xueyang Wang, Sateesh Addepalli, Ramesh Karri:
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks. VLSID 2016: 587-588 - Shankarayya G. Kambalimath, Prem C. Pandey, Pandurangarao N. Kulkarni, Shivaling S. Mahant-Shetti, Sangamesh G. Hiremath:
FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio Input. VLSID 2016: 579-580 - Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID 2016: 595-596 - Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSID 2016: 475-480 - Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar:
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. VLSID 2016: 409-414 - Manchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi:
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard. VLSID 2016: 581-582 - Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha:
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. VLSID 2016: 191-195 - Sandip Kundu, Omer Khan:
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. VLSID 2016: 12-13 - Abishek Thekkeyil Kunnath, Bibhudatta Sahoo:
A Digitally Assisted Radiation Hardened Current Steering DAC. VLSID 2016: 559-560 - William Lee, Tannu Sharma, Kenneth S. Stevens:
Path Based Timing Validation for Timed Asynchronous Design. VLSID 2016: 511-516 - Manas Kumar Lenka, Akash Agrawal, Vishal Khatri, Gaurab Banerjee:
A Wide-Band Receiver Front-End with Programmable Frequency Selective Input Matching. VLSID 2016: 168-173 - Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Invariant Checking for Iterative Solvers. VLSID 2016: 481-486 - Vinaya M. M., Roy Paily, Anil Mahanta:
Power Optimization of LNA for LTE Receiver. VLSID 2016: 162-167