- 1999
- Chanyutt Arjhan, Raghvendra G. Deshmukh:
A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. Asian Test Symposium 1999: 127-132 - Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther:
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. Asian Test Symposium 1999: 321-326 - Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268 - Serge N. Demidenko, Kenneth V. Lever:
Accelerating Test Data Processin. Asian Test Symposium 1999: 113- - Abderrahim Doumar, Hideo Ito:
Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium 1999: 369-374 - Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD. Asian Test Symposium 1999: 95-100 - Jianhua Gao, Shihuang Shao:
Fault-Tolerant Strategies and Their Design Methods for Application Software. Asian Test Symposium 1999: 214-217 - Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 - Ad J. van de Goor, J. E. Simonse:
Defining SRAM Resistive Defects and Their Simulation Stimuli. Asian Test Symposium 1999: 33-40 - Said Hamdioui, Ad J. van de Goor:
March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium 1999: 53- - Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium 1999: 25- - Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146 - Junichi Hirase, Naoki Shindou, Kouji Akahori:
Scan Chain Diagnosis Using IDDQ Current Measurement. Asian Test Symposium 1999: 153-157 - Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki:
Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Asian Test Symposium 1999: 13-19 - Ian Ho, Jin-Cherng Lin:
Generating Test Cases for Real-Time Software by Time Petri Nets Model. Asian Test Symposium 1999: 295-300 - Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara:
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium 1999: 192- - Tsung-Chu Huang, Kuen-Jong Lee:
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320 - Zulan Huang, Yizheng Ye, Zhigang Mao:
A New Algorithm for Retiming-Based Partial Scan. Asian Test Symposium 1999: 327- - Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma:
Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. Asian Test Symposium 1999: 239- - Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 147-152 - Abhijit Jas, Kartik Mohanram, Nur A. Touba:
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275- - Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko:
On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. Asian Test Symposium 1999: 20-24 - Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium 1999: 121-126 - Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium 1999: 158-163 - Abdelhakim Khouas, Mohamed Dessouky, Anne Derieux:
Optimized Statistical Analog Fault Simulation. Asian Test Symposium 1999: 227-232 - Youngchul Kim, C. Robert Carlson:
Scenario Based Integration Testing for Object-Oriented Software Development. Asian Test Symposium 1999: 283-288 - M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor:
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. Asian Test Symposium 1999: 185-191 - Hsing-Chung Liang, Chung-Len Lee:
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. Asian Test Symposium 1999: 173-178 - Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu:
Defect Level Prediction Using Multi-Model Fault Coverage. Asian Test Symposium 1999: 301- - Huaikou Miao, Xiaolei Gao, Ling Liu:
An Approach to Testing the Nonexistence of Initial State in Z Specifications. Asian Test Symposium 1999: 289-294
