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Chung-Len Lee
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Chung-Len Lee 0001 (aka: Chung Len Lee 0001) — Peking University Shenzhen Graduate School, Key Lab of Integrated Microsystems, China (and 1 more)
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2010 – 2019
- 2014
- [j4]Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou:
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2216-2220 (2014) - 2011
- [j3]Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee:
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. IEICE Trans. Electron. 94-C(6): 1112-1119 (2011)
2000 – 2009
- 2008
- [c11]Jian Ruan, Chung-Len Lee:
A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. DELTA 2008: 99-102 - [c10]Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee:
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS 2008: 3426-3429 - 2005
- [j2]Ming Shae Wu, Chung-Len Lee:
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults. IEEE Des. Test Comput. 22(2): 160-169 (2005) - [c9]Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu:
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. Asian Test Symposium 2005: 106-111 - 2004
- [c8]Chung Liang Chen, Chung-Len Lee, Ming Shae Wu:
A New Path Delay Test Scheme Based on Path Delay Inertia. Asian Test Symposium 2004: 140-144 - 2003
- [c7]Chin-Cheng Tsai, Chung-Len Lee:
An On-Chip Jitter Measurement Circuit for the PLL. Asian Test Symposium 2003: 332-335 - 2001
- [c6]Tek Jau Tan, Chung-Len Lee:
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. VTS 2001: 158-162 - 2000
- [j1]Hsing-Chung Liang, Chung-Len Lee:
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. J. Inf. Sci. Eng. 16(5): 687-702 (2000)
1990 – 1999
- 1999
- [c5]Hsing-Chung Liang, Chung-Len Lee:
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. Asian Test Symposium 1999: 173-178 - 1995
- [c4]Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-190 - [c3]Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang:
On Designing of 4-Valued Memory with Double-Gate TFT. ISMVL 1995: 187-193 - 1994
- [c2]Yeong-Jar Chang, Chung-Len Lee:
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. ISMVL 1994: 35-41 - 1991
- [c1]Wen Ching Wu, Chung-Len Lee:
A Probabilistic Testability Measure for Delay Faults. DAC 1991: 440-445
Coauthor Index
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