Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A VLSI Architecture with Multiple Fast Store-Based Block Parallel ..."

Kazuhiro Nakamura et al. (2012)

> Home

Details and statistics

DOI: 10.1587/TRANSELE.E95.C.456

access: closed

type: Journal Article

metadata version: 2020-12-29

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/NakamuraSYTT12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/NakamuraSYTT12
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. 95-C(4): 456-467 (2012)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.