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ORCID16th IEEE Symposium on Computer Arithmetic 2003: Santiago de Compostela, Spain
- 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain. IEEE Computer Society 2003, ISBN 0-7695-1894-X
Keynote Talk
- David W. Matula:
Computer Arithmetic - An Algorithm Engineer's Perspective. 2-
Multiplication
- Zhijun Huang, Milos D. Ercegovac:
High-Performance Left-to-Right Array Multiplier Design. 4-11 - Dimitri Tan, Albert Danysh, Michael J. Liebelt:
Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation. 12-19 - Nicolas Boullis, Arnaud Tisserand:
Some Optimizations of Hardware Multiplication by Constant Matrices. 20-27 - Serdar Süer Erdem, Çetin Kaya Koç
:
A Less Recursive Variant of Karatsuba-Ofman Algorithm for Multiplying Operands of Size a Power of Two. 28-
Division
- Peter Kornerup:
Revisiting SRT Quotient Digit Selection. 38-45 - Mark McCann, Nicholas Pippenger:
SRT Division Algorithms as Dynamical Systems. 46-53 - Eric Rice, Richard Hughey:
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm. 54-62 - David W. Matula, Alex Fit-Florea:
Prescaled Integer Division. 63-
Floating Point
- Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong:
Hardware Implementations of Denormalized Numbers. 70-78 - Sylvie Boldo, Marc Daumas:
Representable Correcting Terms for Possibly Underflowing Floating Point Operations. 79-86 - Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess:
High Performance Floating-Point Unit with 116 Bit Wide Divider. 87-94 - Hossam A. H. Fahmy, Michael J. Flynn:
The Case for a Redundant Format in Floating Point Arithmetic. 95-
Decimal Arithmetic and Revisions to the IEEE 754 Standard
- Michael F. Cowlishaw:
Decimal Floating-Point: Algorism for Computers. 104-111 - Eric M. Schwarz:
Panel: Revisions to the IEEE 754 Standard for Floating-Point Arithmetic. 112-
Elementary Functions
- Jean-Michel Muller:
"Partially Rounded" Small-Order Approximations for Accurate, Hardware-Oriented, Table-Based Methods. 114-121 - Cristina Iordache, Ping Tak Peter Tang:
An Overview of Floating-Point Support and Math Library on the Intel XScaleTM Architecture. 122-128 - Ren-Cang Li, Sylvie Boldo, Marc Daumas:
Theorems on Efficient Argument Reductions. 129-136 - Peter W. Markstein:
Accelerating Sine and Cosine Evaluation with Compiler Assistance. 137-
Testing and Error Analysis
- Damien Stehlé, Vincent Lefèvre, Paul Zimmermann:
Worst Cases and Lattice Reduction. 142-147 - John Harrison:
Isolating Critical Cases for Reciprocals Using Integer Factorization. 148-157 - Avi Ziv, Merav Aharoni, Sigal Asaf:
Solving Range Constraints for Binary Floating-Point Instructions. 158-164 - Guy Even, Peter-Michael Seidel, Warren E. Ferguson:
A Parametric Error Analysis of Goldschmidt?s Division Algorithm. 165-
Cryptography
- Amir K. Daneshbeh, M. Anwarul Hasan:
A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m). 174-180 - Jean-Claude Bajard, Laurent Imbert, Christophe Nègre, Thomas Plantard:
Efficient Multiplication in GF(pk) for Elliptic Curve Cryptography. 181-187 - Arash Reyhani-Masoleh, M. Anwarul Hasan:
Low Complexity Sequential Normal Basis Multipliers over GF(2m). 188-195 - Soonhak Kwon:
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II. 196-
Powering, Multiplication, and Counters
- José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Iterative Algorithm for Powering Computation. 204-211 - Christiane Frougny, Athasit Surarerks:
On-Line Multiplication in Real and Complex Base. 212-219 - Marcelo E. Kaihara, Naofumi Takagi:
A VLSI Algorithm for Modular Multiplication/Division. 220-227 - Israel Koren, Yaron Koren, Bejoy G. Oomman:
Saturating Counters: Application and Design Alternatives. 228-
Number Systems
- Khan A. Wahid, Vassil S. Dimitrov, Graham A. Jullien:
Error-Free Arithmetic for Discrete Wavelet Transforms Using Algebraic Integers. 238-244 - Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis:
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. 245-252 - Mark G. Arnold, Jesus Garcia, Michael J. Schulte:
The Interval Logarithmic Number System. 253-261 - Neil Burgess:
Scaling an RNS Number Using the Core Function. 262-
Modeling and Design of Arithmetic Components
- Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. 272-279 - Vojin G. Oklobdzija, Ram Krishnamurthy:
Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. 280
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