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ORCIDAmitava Majumdar 0002
Person information
- affiliation: Xilinx Inc., USA
- affiliation: AMD Inc., USA
Other persons with the same name
- Amitava Majumdar 0001
![[0000-0002-0860-6686]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-0860-6686")
(aka: Amit Majumdar 0001) — San Diego Supercomputer Center, San Diego, CA, USA (and 1 more)
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Journal Articles
- 2000
[j5]Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar:
Test-set partitioning for multi-weighted random LFSRs. Integr. 30(1): 65-75 (2000)- 1996
- [j4]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
On the Use of Counters for Reproducing Deterministic Test Sets. IEEE Trans. Computers 45(12): 1405-1419 (1996) - 1993
- [j3]Amitava Majumdar, Sarma Sastry:
Probabilistic characterization of controllability in general homogeneous circuits. Comput. Aided Des. 25(2): 76-93 (1993) - 1991
- [j2]Sarma Sastry, Amitava Majumdar:
Test efficiency analysis of random self-test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3): 390-398 (1991) - 1990
- [j1]Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer:
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. IEEE Trans. Computers 39(2): 269-276 (1990)
Conference and Workshop Papers
- 2019
- [c28]Hans Martin von Staudt, Amit Majumdar, Bill Taylor, Jennifer Kitchen:
Innovative Design for Test in State-of-the-Art Analog Systems. VTS 2019: 1 - 2018
- [c27]Amitava Majumdar, Balakrishna Jayadev:
Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. ATS 2018: 36-41 - [c26]Nanqi Liu, Shravan K. Chaganti, Zhiqiang Liu, Degang Chen, Amitava Majumdar:
Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus. ISCAS 2018: 1-5 - 2017
- [c25]Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin:
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. ATS 2017: 139-144 - [c24]Da Cheng, Amitava Majumdar, Xiaobao Wang, Nui Chong:
Field profiling & monitoring of payload transistors in FPGAs. IOLTS 2017: 180-185 - [c23]Zhiqiang Liu, Nanqi Liu, Shravan K. Chaganti, Degang Chen, Amitava Majumdar:
A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection. ISCAS 2017: 1-4 - [c22]Yiorgos Makris, Srivaths Ravi, Amit Majumdar:
Foreword. VTS 2017: 1-2 - 2016
- [c21]Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar:
Application debug in FPGAs in the presence of multiple asynchronous clocks. FPT 2016: 189-192 - [c20]Mike Ricchetti, Eric Rentschler, Amit Majumdar, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar:
Special panel session IIB: "System validation and silicon debug - Is standardization possible?". VTS 2016: 1 - 2014
- [c19]Richard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar:
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies. ETS 2014: 1-6 - [c18]John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar:
Innovative practices session 3C: Solving today's test challenges. VTS 2014: 1 - [c17]Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang:
Innovative practices session 4C: Disruptive solutions in the non-digital world. VTS 2014: 1 - [c16]Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran:
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS 2014: 1 - 2012
- [c15]Yang Zhao, Lisa Grenier, Amitava Majumdar:
Power Characterization of Embedded SRAMs for Power Binning. VTS 2012: 203-208 - 2011
- [c14]Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg:
Special session 5B: Panel How much toggle activity should we be testing with? VTS 2011: 114 - [c13]Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou:
A Novel mechanism for speed characterization during delay test. VTS 2011: 116-121 - 2009
- [c12]Arani Sinha, Amitava Majumdar, Vasu Ganti:
Panel: Analog Characterization and Test: The Long Road to Realization. VTS 2009: 337 - 2006
- [c11]Amitava Majumdar, Wei-Yu Chen, Jun Guo:
Hold time validation on silicon and the relevance of hazards in timing analysis. DAC 2006: 326-331 - 2003
- [c10]Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan:
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. ITC 2003: 961-970 - 2002
- [c9]Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar:
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. ITC 2002: 726-735 - 2001
- [c8]Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar:
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529 - 1998
- [c7]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
On-Chip Test Embedding for Multi-Weighted Random LFSRs. DFT 1998: 135- - [c6]Amitava Majumdar, Michio Komoda, Tim Ayres:
Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. VTS 1998: 86-91 - 1996
- [c5]Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
Deterministic Test Pattern Reproduction by a Counter. ED&TC 1996: 37-41 - 1993
- [c4]Amitava Majumdar, Sarma Sastry:
Statistical Analysis of Controllability. VLSI Design 1993: 55-60 - 1992
- [c3]Amitava Majumdar, Sarma Sastry:
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. DAC 1992: 341-346 - 1991
- [c2]Sarma Sastry, Amitava Majumdar:
A Branching Process Model for Observability Analysis of Combinational Circuits. DAC 1991: 452-457 - 1988
- [c1]Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra:
Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. ICCD 1988: 514-519
Coauthor Index
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