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ORCIDGinés Doménech-Asensi
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- affiliation: Universidad Politecnica de Cartagena, Spain
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Journal Articles
- 2022
[j12]Ginés Doménech-Asensi
, María-Dolores Cano, Víctor Morales-Esteras:
On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices. J. Signal Process. Syst. 94(3): 293-304 (2022)- 2021
- [j11]José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino:
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. 40(2): 515-528 (2021) - 2020
- [j10]Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López:
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17(2): 371-382 (2020) - 2018
- [j9]Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud:
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46(9): 1690-1702 (2018) - 2015
- [j8]Julio Illade-Quinteiro, Víctor M. Brea, Paula López Martinez, Diego Cabello, Ginés Doménech-Asensi:
Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise. Sensors 15(3): 4624-4642 (2015) - 2014
- [j7]Francisco J. Fernández-Luque, Félix L. Martínez, Ginés Doménech, Juan Zapata-Pérez, Ramón Ruiz:
Ambient assisted living system with capacitive occupancy sensor. Expert Syst. J. Knowl. Eng. 31(4): 378-388 (2014) - 2013
- [j6]Francisco J. Fernández-Luque, David Pérez, Félix Martínez, Ginés Doménech, Isabel Navarrete, Juan Zapata-Pérez, Ramón Ruiz:
An energy efficient middleware for an ad-hoc AAL wireless sensor network. Ad Hoc Networks 11(3): 907-925 (2013) - [j5]Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino:
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. 41(7): 732-742 (2013) - 2012
- [j4]Roberto Paoli, Francisco J. Fernández-Luque, Ginés Doménech, Félix Martínez, Juan Zapata-Pérez, Ramón Ruiz:
A system for ubiquitous fall monitoring at home via a wireless sensor network and a wearable mote. Expert Syst. Appl. 39(5): 5566-5575 (2012) - 2011
- [j3]María-Dolores Cano, Ginés Doménech-Asensi:
A secure energy-efficient m-banking application for mobile devices. J. Syst. Softw. 84(11): 1899-1909 (2011) - 2010
- [j2]José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi:
Fuzzy logic technique for accurate analog circuits macromodel sizing. Int. J. Circuit Theory Appl. 38(3): 307-319 (2010) - 2007
- [j1]Ginés Doménech-Asensi, Juan Hinojosa, Juan Martínez-Alajarín:
A behavioral model development methodology for microwave components and integration in VHDL-AMS. Microelectron. J. 38(4-5): 489-495 (2007)
Conference and Workshop Papers
- 2023
- [c27]Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid:
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS 2023: 1-5 - 2021
- [c26]Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. DCIS 2021: 1-5 - 2020
- [c25]Ginés Doménech-Asensi, Tom J. Kazmierski:
High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. DATE 2020: 646-649 - [c24]José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez:
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS 2020: 1-5 - [c23]Ginés Doménech-Asensi, Tom J. Kazmierski:
Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. ISCAS 2020: 1-5 - 2019
- [c22]Ginés Doménech-Asensi, Tom J. Kazmierski:
Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. FDL 2019: 1-4 - [c21]Ginés Doménech-Asensi, Tom J. Kazmierski:
An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. ISCAS 2019: 1-5 - [c20]Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. ISCAS 2019: 1-5 - 2018
- [c19]Juan Francisco Inglés-Romero, Ginés Doménech-Asensi, María-Dolores Cano-Baños, Víctor Morales-Esteras:
Traffic Metrics at Urban Intersections using a Low-Cost Image Processing Approach. ICDSC 2018: 9:1-9:7 - [c18]Ricardo Carmona-Galán, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Paula López Martinez, Víctor Manuel Brea Sánchez, Diego Cabello Ferrer, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez:
Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. ICDSC 2018: 24:1-24:2 - [c17]Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
FPGA real time synthesis of simplified SIFT algorithm. ICDSC 2018: 26:1-26:2 - 2017
- [c16]José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst:
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS 2017: 1-4 - [c15]Ginés Doménech-Asensi, Tom J. Kazmierski:
Generation of new power processing structures exploiting genetic programming. ISIE 2017: 729-732 - 2016
- [c14]Ramon Sanchez-Iborra, Juan F. Inglés-Romero, Ginés Doménech-Asensi, José-Luis Moreno-Cegarra, María-Dolores Cano:
Proactive Intelligent System for Optimizing Traffic Signaling. DASC/PiCom/DataCom/CyberSciTech 2016: 544-551 - 2014
- [c13]Pablo Leyva, Ginés Doménech-Asensi, F. Javier Garrigós, Julio Illade-Quinteiro, Víctor M. Brea, Paula López, Diego Cabello:
Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. FPL 2014: 1-4 - 2013
- [c12]Víctor M. Brea, Manuel Suarez, J. Illade-Quinteiro, Paula López, Diego Cabello, Ginés Doménech-Asensi:
Voltage boosters for on-chip solar cells on focal-plane processors. ICECS 2013: 393-396 - 2012
- [c11]Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez:
A fourth order CMOS band pass filter for PIR sensors. ICECS 2012: 268-271 - 2009
- [c10]José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino:
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE 2009: 369-373 - 2008
- [c9]Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid:
Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS 2008: 508-511 - 2007
- [c8]Juan Hinojosa, Ginés Doménech-Asensi:
Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications. ECCTD 2007: 767-770 - [c7]José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi:
Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. IWINAC (2) 2007: 19-27 - 2006
- [c6]Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud:
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL 2006: 1-5 - 2005
- [c5]Ginés Doménech, Juan Hinojosa, Juan Martínez-Alajarín, F. Javier Garrigós:
Empirical Model Generations of Microwave Devices Exploiting Linear Regression Models. ISCC 2005: 257-262 - [c4]F. Javier Garrigós, Juan Hinojosa, Juan Martínez-Alajarín, Ginés Doménech:
Empirical Model Optimization of Microwave Devices Exploiting Genetic Algorithms. ISCC 2005: 263-268 - [c3]Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino:
Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) 2005: 357-365 - 2003
- [c2]Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid:
Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) 2003: 25-32 - 2002
- [c1]J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski:
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. ISCAS (4) 2002: 77-80
Coauthor Index
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last updated on 2024-07-09 05:13 CEST by the dblp team
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