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"FPGA real time synthesis of simplified SIFT algorithm."

Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi (2018)

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DOI: 10.1145/3243394.3243706

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-21

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  dblp key:
  - conf/icdsc/Rubio-IbanezMD18
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  - https://dblp.org/rec/conf/icdsc/Rubio-IbanezMD18
Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi:
FPGA real time synthesis of simplified SIFT algorithm. ICDSC 2018: 26:1-26:2

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