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"Automated high level synthesis of hardware building blocks present in ..."

J. A. López et al. (2002)

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DOI: 10.1109/ISCAS.2002.1010392

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-28

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J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski:
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. ISCAS (4) 2002: 77-80

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