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ORCIDYoung Jun Park
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2020 – today
- 2023
[j4]Myeong-Jae Park
, Jinhyung Lee, Kyungjun Cho, Ji Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee, Jieun Jang, Joohwan Cho:
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. IEEE J. Solid State Circuits 58(1): 256-269 (2023)- 2022
- [c14]Myeong-Jae Park, Ho Sung Cho, Tae-Sik Yun, Sangjin Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Seung Geun Baek, Kyo Yun Lee, Sang Hun Lee, Woo Sung We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seung Min Yang, Gunho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, Taejin Hwang, Junghyun Shin, Yunho Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, Junhyun Chun, Joohwan Cho:
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. ISSCC 2022: 444-446 - 2020
- [j3]Hyo Seon Park, Jung Hwan An, Young Jun Park, Byung Kwan Oh:
Convolutional neural network-based safety evaluation method for structures with dynamic responses. Expert Syst. Appl. 158: 113634 (2020) - [c13]Dong-Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Wooyoung Lee, Tae-Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park, Seokwoo Choi, Young Jun Park, Chang Kwon Lee, Chunseok Jeong, Jae-Seung Lee, Sang Hun Lee, Woo Sung We, Jong Chan Yun, Doobock Lee, Junghyun Shin, Seungchan Kim, Junghwan Lee, Jiho Choi, Yucheon Ju, Myeong-Jae Park, Kang Seol Lee, Youngdo Hur, Daeyong Shim, Sangkwon Lee, Junhyun Chun, Kyowon Jin:
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. ISSCC 2020: 334-336
2010 – 2019
- 2018
- [j2]Young Jun Park, Parth Parekh, Fei Yuan:
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. Microelectron. J. 81: 179-191 (2018) - 2017
- [j1]Young Jun Park, Fei Yuan:
Two-step pulse-shrinking time-to-digital converter. Microelectron. J. 60: 45-54 (2017) - [c12]Syed Adil Ali Shah, Young Jun Park, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Danial Khan, Kang-Yoon Lee:
A high-efficiency active rectifier by using zero current sensing and deglitch circuit for inductive coupling receiver. ISOCC 2017: 206-207 - [c11]Zaffar Hayat Nawaz Khan, Danial Khan, Nabeel Ahmad, Hamed Abbasizadeh, Syed Adil Ali Shah, Young Jun Park, Kang-Yoon Lee:
6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer. ISOCC 2017: 208-209 - [c10]Khuram Shehzad, Hye-Young Kang, Deeksha Verma, Young Jun Park, Kang-Yoon Lee:
Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications. ISOCC 2017: 224-225 - [c9]Young Jun Park, Fei Yuan:
Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. MWSCAS 2017: 679-682 - [c8]Young Jun Park, Fei Yuan:
1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator. MWSCAS 2017: 1005-1008 - [c7]Young Jun Park, Fei Yuan:
All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator. MWSCAS 2017: 1513-1516 - 2016
- [c6]Young Jun Park, Durand Jarrett-Amor, Fei Yuan:
Time integrator for mixed-mode signal processing. ISCAS 2016: 826-829 - [c5]Durand Jarrett-Amor, Young Jun Park, Fei Yuan:
Time-mode techniques for fast-locking phase-locked loops. ISCAS 2016: 1790-1793 - 2015
- [c4]Young Jun Park, Fei Yuan:
0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme. MWSCAS 2015: 1-4 - [c3]Young Jun Park, Fei Yuan:
A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS. MWSCAS 2015: 1-4 - [c2]Hyun Woo Kim, Young Jun Park, Jun Won Yoon, Seul Jung:
Line tracking control demonstration of a master-slave balancing mobile robot. URAI 2015: 355 - 2014
- [c1]Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, Jang Hwan Cho, Ki Hun Kwon, Min Jeong Kim, Jaejin Lee, Kunwoo Park, Byong-Tae Chung, Sung-Joo Hong:
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. ISSCC 2014: 432-433
Coauthor Index
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