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"Formal Verification of VHDL Descriptions in the Prevail Environment."

Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem (1992)

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DOI: 10.1109/54.143145

access: closed

type: Journal Article

metadata version: 2024-05-07

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/journals/dt/BorrionePS92
Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992)

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