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Sandeep Kumar Goel
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Publications
- 2015
- [j9]Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers 64(12): 3335-3347 (2015) - 2014
- [j8]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - 2012
- [c32]Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl:
EDA solutions to new-defect detection in advanced process technologies. DATE 2012: 123-128 - [c30]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10 - 2011
- [j7]Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree:
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1705-1718 (2011) - [c29]Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel:
Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400 - [c28]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c27]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c26]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - 2010
- [c24]Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree:
Test-architecture optimization for TSV-based 3D stacked ICs. ETS 2010: 24-29 - 2009
- [j6]Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty:
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009) - 2007
- [i1]Sandeep Kumar Goel, Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. CoRR abs/0710.4687 (2007) - 2006
- [c18]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290 - 2005
- [c16]Sandeep Kumar Goel, Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE 2005: 44-49 - [c15]Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Test scheduling for modular SOCs in an abort-on-fail environment. ETS 2005: 8-13 - 2004
- [c13]Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk:
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE 2004: 108-113 - [c12]Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre:
User-constrained test architecture design for modular SOC testing. ETS 2004: 80-85 - [c11]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212 - 2003
- [j3]Sandeep Kumar Goel, Erik Jan Marinissen:
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electron. Test. 19(4): 425-435 (2003) - [j2]Sandeep Kumar Goel, Erik Jan Marinissen:
SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003) - [c10]Sandeep Kumar Goel, Erik Jan Marinissen:
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE 2003: 10738-10741 - [c9]Sandeep Kumar Goel, Erik Jan Marinissen:
Control-aware test architecture design for modular SOC testing. ETW 2003: 57-62 - 2002
- [c8]Sandeep Kumar Goel, Erik Jan Marinissen:
A novel test time reduction algorithm for test architecture design for core-based system chips. ETW 2002: 7-12 - [c6]Sandeep Kumar Goel, Erik Jan Marinissen:
Effective and Efficient Test Architecture Design for SOCs. ITC 2002: 529-538 - [c3]Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168 - [c2]Sandeep Kumar Goel, Erik Jan Marinissen:
Cluster-Based Test Architecture Design for System-on-Chip. VTS 2002: 259-264 - 2000
- [c1]Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel:
Wrapper design for embedded core test. ITC 2000: 911-920
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