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ORCIDYi Kang
Publications
- 2024
[j27]Haitao Du
, Yuhan Qin, Song Chen, Yi Kang:
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration. ACM Trans. Archit. Code Optim. 21(2): 34 (2024)- [j26]Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang:
Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity. IEEE Trans. Computers 73(1): 152-163 (2024) - [j25]Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang:
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1456-1469 (2024) - [j24]Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang:
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3754-3763 (2024) - [j23]Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang:
AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems. ACM Trans. Design Autom. Electr. Syst. 29(1): 8:1-8:19 (2024) - [j22]Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, Yi Kang:
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. ACM Trans. Design Autom. Electr. Syst. 29(3): 56:1-56:17 (2024) - [c39]Bo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang:
Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner. DATE 2024: 1-6 - [c38]Wendi Sun, Wenhao Sun, Yifan Wang, Yi Kang, Song Chen:
Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration. ACM Great Lakes Symposium on VLSI 2024: 144-150 - [i10]Mengke Ge, Junpeng Wang, Binhan Chen, Yingjian Zhong, Haitao Du, Song Chen, Yi Kang:
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems. CoRR abs/2403.15069 (2024) - 2023
- [j17]Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu:
Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems. IEEE Trans Autom. Sci. Eng. 20(1): 74-87 (2023) - [j15]Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang:
Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2221-2225 (2023) - [j14]Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, Yi Kang:
BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3054-3058 (2023) - [j13]Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang:
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. ACM Trans. Design Autom. Electr. Syst. 28(1): 7:1-7:21 (2023) - [j12]Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang:
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. ACM Trans. Design Autom. Electr. Syst. 28(3): 36:1-36:30 (2023) - [j11]Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. ACM Trans. Design Autom. Electr. Syst. 28(6): 103:1-103:26 (2023) - [j10]Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen, Yi Kang:
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 470-483 (2023) - [c31]Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang:
An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory. BioCAS 2023: 1-5 - [c30]Bin Zhang, Haitao Du, Song Chen, Yi Kang:
GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm. CF 2023: 33-41 - [c29]Zetao Guo, Junpeng Wang, Song Chen, Yi Kang:
A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution. ICTA 2023: 122-123 - [i9]Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang:
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. CoRR abs/2302.00201 (2023) - [i8]Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang:
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM. CoRR abs/2305.19041 (2023) - [i7]Xiaobing Ni, Jiaheng Ruan, Mengke Ge, Wendi Sun, Song Chen, Yi Kang:
BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array. CoRR abs/2310.06613 (2023) - [i6]Zihao Xuan, Song Chen, Yi Kang:
AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect. CoRR abs/2312.11836 (2023) - [i5]Wenhao Sun, Wendi Sun, Song Chen, Yi Kang:
IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product. CoRR abs/2312.12766 (2023) - [i4]Qi Xu, Lijie Wang, Jing Wang, Song Chen, Lin Cheng, Yi Kang:
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits. CoRR abs/2312.14405 (2023) - 2022
- [j9]Ke Hu, Wenhao Sun, Zhongbo Nie, Ran Cheng, Song Chen, Yi Kang:
Real-time infrared small target detection network and accelerator design. Integr. 87: 241-252 (2022) - [j8]Qi Xu, Wenhao Sun, Song Chen, Yi Kang, Xiaoqing Wen:
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1196-1208 (2022) - [j7]Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen:
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3182-3187 (2022) - [j6]Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen:
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3492-3502 (2022) - [j5]Mengke Ge, Xiaobing Ni, Song Chen, Yi Kang:
Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1552-1556 (2022) - [j4]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. ACM Trans. Design Autom. Electr. Syst. 27(1): 9:1-9:30 (2022) - [c26]Qiaojun Wu, Yuan Li, Song Chen, Yi Kang:
DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection. DMBD (1) 2022: 137-151 - [c23]Yifan Song, Shunpeng Zhao, Song Chen, Yi Kang:
SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer. ICTA 2022: 56-57 - [c22]Bin Zhang, Haitao Du, Song Chen, Yi Kang:
PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering. ISCAS 2022: 2675-2679 - [c20]Yuan Li, Qiaojun Wu, Song Chen, Yi Kang:
Multi-scale Lightweight Neural Network for Real-Time Object Detection. PRICAI (3) 2022: 199-211 - [i3]Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Junpeng Wang, Yi Kang, Song Chen:
Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks. CoRR abs/2202.00389 (2022) - [i2]Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. CoRR abs/2212.05397 (2022) - 2021
- [c19]Mingjian Sun, Yuan Li, Song Chen, Yi Kang:
A Low Power Branch Prediction for Deep Learning on RISC-V Processor. ASAP 2021: 203-206 - [c15]Lei Ding, Haitao Du, Song Chen, Yi Kang:
A Low-latency NoC Router Priority Scheme for BFS algorithm. ICTA 2021: 271-272 - [c14]Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang:
A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier. NVMSA 2021: 1-6 - [i1]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips. CoRR abs/2108.01298 (2021) - 2020
- [c13]Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang:
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems. ACM Great Lakes Symposium on VLSI 2020: 303-308 - 2019
- [c12]Baicheng Liu, Song Chen, Yi Kang, Feng Wu:
An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network. ASICON 2019: 1-4 - [c11]Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen, Yi Kang, Feng Wu:
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN. ASICON 2019: 1-4
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last updated on 2024-08-23 19:21 CEST by the dblp team
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