"Reducing Test Power, Time and Data Volume in SoC Testing Using Selective ..."

Shervin Sharifi et al. (2003)

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DOI: 10.1109/DFTVS.2003.1250131

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360

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