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Publication search results
found 35 matches
- 2007
- Ben Bennetts:
Electronics Design-for-Test: Past, Present and Future. ETS 2007: 4 - Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. ETS 2007: 179-184 - Philippe Cauvet, Serge Bernard, Michel Renovell:
System-in-Package, a Combination of Challenges and Solutions. ETS 2007: 193-199 - Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson:
A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus. ETS 2007: 105-110 - Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS 2007: 77-84 - Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab:
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. ETS 2007: 173-178 - Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero:
PPM Reduction on Embedded Memories in System on Chip. ETS 2007: 85-90 - Stefan Holst, Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis without Fault Dictionaries. ETS 2007: 7-12 - Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS 2007: 35-42 - Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara:
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. ETS 2007: 117-124 - Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS 2007: 211-216 - Ivo Koren, Frank Demmerle, Roland May, Martin Kaibel, Sebastian Sattler:
FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests. ETS 2007: 43-48 - Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel:
Computation and Application of Absolute Dominators in Industrial Designs. ETS 2007: 137-144 - Shaji Krishnan, Rene Jonker, Leon van de Logt:
Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives. ETS 2007: 55-62 - Carlos Arthur Lang Lisbôa, Marcelo Ienczczak Erigson, Luigi Carro:
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies. ETS 2007: 165-172 - Klaus Luther:
Embedded Tutorial: IC Test Cost Benchmarking. ETS 2007: 200 - Peter C. Maxwell:
Wafer Level Reliability Screens. ETS 2007: 201 - Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
Selecting Power-Optimal SBST Routines for On-Line Processor Testing. ETS 2007: 111-116 - Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Digital Generation of Signals for Low Cost RF BIST. ETS 2007: 49-54 - Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS 2007: 97-104 - Nicola Nicolici, Xiaoqing Wen:
Embedded Tutorial on Low Power Test. ETS 2007: 202-210 - Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. ETS 2007: 91-96 - Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Based on Subsets of Faults. ETS 2007: 151-158 - Jaan Raik, Raimund Ubar, Vineeth Govind:
Test Configurations for Diagnosing Faulty Links in NoC Switches. ETS 2007: 29-34 - Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis. ETS 2007: 13-20 - Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro:
A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter. ETS 2007: 21-28 - Rene Segers:
If It's All about Yield, Why Talk about Testing? ETS 2007: 3 - Luca Sterpone, Massimo Violante:
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. ETS 2007: 159-164 - Stephen K. Sunter, Aubin Roy:
Purely Digital BIST for Any PLL or DLL. ETS 2007: 185-192 - Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware:
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. ETS 2007: 145-150
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