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Vineeth Govind
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2010 – 2019
- 2015
- [c5]Pietro Saltarelli, Behrad Niazmand
, Jaan Raik
, Vineeth Govind, Thomas Hollstein
, Gert Jervan
, Ranganathan Hariharan:
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. NOCS 2015: 6:1-6:8 - 2012
- [c4]Jaan Raik
, Vineeth Govind:
Low-area boundary BIST architecture for mesh-like network-on-chip. DDECS 2012: 95-100 - [c3]Hervé Tatenguem
, Alessandro Strano, Vineeth Govind, Jaan Raik
, Davide Bertozzi:
Ultra-low latency NoC testing via pseudo-random test pattern compaction. ISSoC 2012: 1-6
2000 – 2009
- 2009
- [j1]Jaan Raik
, Vineeth Govind, Raimund Ubar
:
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. 3(5): 476-486 (2009) - 2007
- [c2]Jaan Raik
, Raimund Ubar
, Vineeth Govind:
Test Configurations for Diagnosing Faulty Links in NoC Switches. ETS 2007: 29-34 - 2006
- [c1]Jaan Raik
, Vineeth Govind, Raimund Ubar
:
An External Test Approach for Network-on-a-Chip Switches. ATS 2006: 437-442
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last updated on 2024-04-24 22:47 CEST by the dblp team
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