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José María Llabería
Person information
- affiliation: Polytechnic University of Catalonia, Barcelona, Spain
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2020 – today
- 2024
- [i3]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería:
Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR abs/2402.00533 (2024) - 2023
- [c45]Carlos Escuin, Fernando García-Redondo
, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas
, Francky Catthoor:
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS 2023: 1-5 - 2022
- [i2]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR abs/2204.03512 (2022) - [i1]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR abs/2204.09504 (2022) - 2021
- [j21]Javier Díaz, Pablo Ibáñez
, Teresa Monreal, Víctor Viñals, José M. Llabería:
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77(10): 11756-11785 (2021)
2010 – 2019
- 2019
- [j20]Javier Díaz, Teresa Monreal
, Pablo Ibáñez
, José M. Llabería
, Víctor Viñals
:
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125: 106-120 (2019) - 2018
- [j19]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro
, Pablo Ibáñez
, Daniel Chaver
, Víctor Viñals, Juan Carlos Saez
, Manuel Prieto-Matías
, Luis Piñuel, Teresa Monreal Arnal
, José María Llabería
:
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61(6): 856-880 (2018) - 2013
- [j18]Jorge Albericio, Pablo Ibáñez
, Víctor Viñals
, José María Llabería
:
Exploiting reuse locality on inclusive shared last-level caches. ACM Trans. Archit. Code Optim. 9(4): 38:1-38:19 (2013) - [c44]Jorge Albericio, Pablo Ibáñez
, Víctor Viñals
, José M. Llabería
:
The reuse cache: downsizing the shared last-level cache. MICRO 2013: 310-321 - 2012
- [j17]Benjamín Sahelices
, Agustín De Dios Hernández, Pablo Ibáñez
, Víctor Viñals Yúfera
, José María Llabería
:
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27(1): 75-91 (2012) - [j16]Jorge Albericio, Ruben Gran Tejero
, Pablo Ibáñez
, Víctor Viñals
, José María Llabería
:
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. 8(4): 19:1-19:20 (2012) - 2011
- [j15]Ana Bosque, Víctor Viñals
, Pablo Ibáñez
, José M. Llabería
:
Filtering directory lookups in CMPs. Microprocess. Microsystems 35(8): 695-707 (2011) - [c43]Ana Bosque, Víctor Viñals
, Pablo Ibáñez
, José María Llabería
:
Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) 2011: 269-281 - 2010
- [c42]Ana Bosque, Víctor Viñals
, Pablo Ibáñez
, José M. Llabería
:
Filtering Directory Lookups in CMPs. DSD 2010: 207-216
2000 – 2009
- 2009
- [j14]Enrique F. Torres, Pablo Ibáñez
, Víctor Viñals Yúfera
, José María Llabería
:
Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58(10): 1307-1320 (2009) - [c41]Benjamín Sahelices
, Pablo Ibáñez
, Víctor Viñals
, José María Llabería
:
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161 - [c40]Ruben Gran Tejero
, Enric Morancho, Àngel Olivé, José María Llabería
:
On reducing misspeculations in a pipelined scheduler. IPDPS 2009: 1-12 - 2007
- [j13]Enric Morancho, José María Llabería
, Àngel Olivé:
A comparison of two policies for issuing instructions speculatively. J. Syst. Archit. 53(4): 170-183 (2007) - [c39]Enric Morancho, José María Llabería
, Àngel Olivé:
On reducing energy-consumption by late-inserting instructions into the issue queue. ISLPED 2007: 371-374 - [c38]Ana Bosque, Pablo Ibáñez
, Víctor Viñals
, Per Stenström, José María Llabería
:
Characterization of Apache web server with Specweb2005. MEDEA@PACT 2007: 65-72 - 2006
- [c37]Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez
, Víctor Viñals, José M. Llabería:
Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484 - [c36]Ruben Gran Tejero
, Enric Morancho, Àngel Olivé, José María Llabería
:
An Enhancement for a Scheduling Logic Pipelined over two Cycles . ICCD 2006: 203-209 - 2005
- [j12]María Jesús Garzarán, Milos Prvulovic, José María Llabería
, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas:
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. 2(3): 247-279 (2005) - [c35]Enrique F. Torres, Pablo Ibáñez
, Víctor Viñals
, José María Llabería
:
Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480 - 2004
- [c34]Enrique F. Torres, Pablo Ibáñez
, Víctor Viñals, José María Llabería:
Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524 - [c33]Enric Morancho, José María Llabería, Àngel Olivé:
A Mechanism for Verifying Data Speculation. Euro-Par 2004: 525-534 - 2003
- [j11]Marta Jiménez, José M. Llabería
, Agustín Fernández:
A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distributed Syst. 14(10): 1006-1020 (2003) - [c32]María Jesús Garzarán, Milos Prvulovic, Víctor Viñals
, José María Llabería
, Lawrence Rauchwerger, Josep Torrellas:
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181 - [c31]Enrique F. Torres, Pablo Ibáñez
, Víctor Viñals, José María Llabería:
Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596 - [c30]María Jesús Garzarán, Milos Prvulovic, José María Llabería
, Víctor Viñals
, Lawrence Rauchwerger, Josep Torrellas:
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202 - 2002
- [j10]Marta Jiménez, José M. Llabería
, Agustín Fernández:
Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. 24(4): 409-453 (2002) - 2001
- [c29]Enric Morancho, José María Llabería, Àngel Olivé:
Recovery Mechanism for Latency Misprediction. IEEE PACT 2001: 118-128 - 2000
- [c28]Enric Morancho, José M. Llabería, Àngel Olivé:
Two-Level Address Storage and Address Prediction (Research Note). Euro-Par 2000: 960-964 - [c27]Marta Jiménez, José M. Llabería, Agustín Fernández:
On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA 2000: 183-194 - [c26]Luis M. Ramos, Pablo E. Ibáñez
, Víctor Viñals
, José M. Llabería
:
Modeling load address behaviour through recurrences. ISPASS 2000: 101-108
1990 – 1999
- 1999
- [j9]Anna M. del Corral
, José M. Llabería
:
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. IEEE Trans. Computers 48(4): 449-456 (1999) - [c25]Enric Morancho, José M. Llabería, Àngel Olivé:
Looking at History to Filter Allocations in Prediction Tables. IEEE PACT 1999: 314-319 - 1998
- [c24]Enric Morancho, José M. Llabería
, Àngel Olivé:
Split Last-Address Predictor. IEEE PACT 1998: 230- - [c23]Marta Jiménez, José M. Llabería, Agustín Fernández:
Performance Evaluation of Tiling for the Register Level. HPCA 1998: 254-265 - [c22]Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho:
A General Algorithm for Tiling the Register Level. International Conference on Supercomputing 1998: 133-140 - [c21]Marta Jiménez, José María Llabería, Agustín Fernández:
Loop bounds computation for multilevel tiling. PDP 1998: 445-452 - [c20]Anna M. del Corral
, José M. Llabería
:
New Access Order to Reduce Inter-Vector-Conflicts. VECPAR 1998: 425-438 - 1996
- [c19]Anna M. del Corral, José M. Llabería:
Increasing the Effective Memory Bandwidth in Multivector Processors. EUROMICRO 1996: 38-45 - [c18]Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho:
A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I 1996: 402-405 - [c17]Anna M. del Corral, José M. Llabería:
Reducing Inter-Vector-Conflicts in Complex Memory Systems. International Conference on Supercomputing 1996: 382-389 - [c16]Anna M. del Corral, José María Llabería:
Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors. SC 1996: 26 - 1995
- [j8]Agustín Fernández, José M. Llabería
, Miguel Valero-García:
Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distributed Syst. 6(8): 832-840 (1995) - [c15]Anna M. del Corral, José M. Llabería:
Access order to avoid inter-vector-conflicts in complex memory systems. IPPS 1995: 404-410 - 1994
- [c14]Anna M. del Corral, José M. Llabería:
Out-of-order access to vector elements in order to reduce conflicts in vector processors. SPDP 1994: 126-134 - 1993
- [j7]Antonio González
, José M. Llabería:
Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers 42(3): 363-371 (1993) - 1992
- [j6]Jordi Cortadella
, José M. Llabería
:
Evaluation of A + B = K Conditions Without Carry Propagation. IEEE Trans. Computers 41(11): 1484-1488 (1992) - [j5]Miguel Valero-García, Juan J. Navarro, José María Llabería
, Mateo Valero
, Tomás Lang:
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. J. VLSI Signal Process. 4(1): 7-25 (1992) - [c13]Alvaro Suárez, José M. Llabería, Agustín Fernández:
Scheduling partitions in systolic algorithms. ASAP 1992: 619-633 - [c12]Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro:
Increasing the Number of Strides for Conflict-Free Vector Access. ISCA 1992: 372-381 - 1991
- [j4]Agustín Fernández, José María Llabería
, Juan J. Navarro, Miguel Valero-García:
Performance evaluation of transputer systems with linear algebra problems. Microprocessing and Microprogramming 32(1-5): 825-832 (1991) - [j3]Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé:
Conflict-Free Strides for Vectors in Matched Memories. Parallel Process. Lett. 1: 95-102 (1991) - [c11]Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García:
Transformation of systolic algorithms for interleaving partitions. ASAP 1991: 56-71 - [c10]Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García:
Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC 1991: 90-99 - [c9]Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero:
On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC 1991: 173-182 - [c8]Jesús Labarta
, Eduard Ayguadé, Jordi Torres
, Mateo Valero, José M. Llabería:
Balanced Loop Partitioning Using GTS. LCPC 1991: 298-312 - 1990
- [c7]Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Implementation of systolic algorithms using pipelined functional units. ASAP 1990: 272-283
1980 – 1989
- 1989
- [c6]Antonio González, José M. Llabería
:
Instruction fetch unit for parallel execution of branch instructions. ICS 1989: 417-426 - [c5]Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Systematic Hardware Adaptation of Systolic Algorithms. ISCA 1989: 96-104 - 1988
- [j2]Antonio González
, José María Llabería
, Jordi Cortadella
:
A mechanism for reducing the cost of branches in RISC architectures. Microprocess. Microprogramming 24(1-5): 565-572 (1988) - 1987
- [j1]Juan J. Navarro, José M. Llabería
, Mateo Valero
:
Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. Computer 20(7): 77-89 (1987) - 1986
- [c4]Juan J. Navarro, José M. Llabería, Mateo Valero:
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP 1986: 676-683 - [c3]Juan J. Navarro, José M. Llabería, Mateo Valero:
Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA 1986: 271-278 - 1985
- [c2]José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta:
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA 1985: 414-421 - 1983
- [c1]Mateo Valero, José María Llabería
, Jesús Labarta, Emilio Sanvicente, Tomás Lang:
A performance evaluation of the multiple bus network for multiprocessor systems. SIGMETRICS 1983: 200-206
Coauthor Index
aka: Víctor Viñals Yúfera
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last updated on 2024-07-15 01:02 CEST by the dblp team
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