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ORCIDJournal of Systems Architecture, Volume 53
Volume 53, Number 1, January 2007
- Lian Li, Jingling Xue
:
Trace-based leakage energy optimisations at link time. 1-20 - Chen-Liang Fang, Deron Liang, Fengyi Lin, Chien-Cheng Lin:
Fault tolerant Web Services. 21-38 - Dongmahn Seo, Joahyoung Lee, Yoon Kim, Changyeol Choi, Manbae Kim, Inbum Jung:
Resource consumption-aware QoS in cluster-based VOD servers. 39-52 - Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj:
An efficient variable partitioning approach for functional decomposition of circuits. 53-67
Volume 53, Numbers 2-3, February-March 2007
- Nadia Nedjah, Luiza de Macedo Mourelle:
Embedded cryptographic hardware. 69-71 - Guerric Meurice de Dormale, Jean-Jacques Quisquater:
High-speed hardware implementations of Elliptic Curve Cryptography: A survey. 72-84 - Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins:
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve. 85-98 - Nadia Nedjah, Luiza de Macedo Mourelle:
Fast hardware for modular exponentiation with efficient exponent pre-processing. 99-108 - Christophe Nègre:
Efficient parallel multiplier in shifted polynomial basis. 109-116 - Florent Bernard:
Scalable hardware implementing high-radix Montgomery multiplication algorithm. 117-126 - Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
Multi-mode operator for SHA-2 hash functions. 127-138 - Konrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin:
Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard. 139-149
Volume 53, Number 4, April 2007
- Tiberiu Seceleanu:
The SegBus platform - architecture and communication mechanisms. 151-169 - Enric Morancho, José María Llabería, Àngel Olivé:
A comparison of two policies for issuing instructions speculatively. 170-183 - Khaled Benkrid, Abdsamad Benkrid, Samir Belkacemi:
Efficient FPGA hardware development: A multi-language approach. 184-209 - Ch. Rambabu, I. Chakrabarti:
An efficient immersion-based watershed transform method and its prototype architecture. 210-226 - Ming-Chien Yang, Jimmy J. M. Tan, Lih-Hsing Hsu:
Highly fault-tolerant cycle embeddings of hypercubes. 227-232 - F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Hardware support for adaptive tessellation of Bézier surfaces based on local tests. 233-250
Volume 53, Numbers 5-6, May-June 2007
- Klaus Waldschmidt, Jan Haase, Werner Grass, Bernhard Sick:
Editorial. 251-252 - Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
Asynchronous arbiter for micro-threaded chip multiprocessors. 253-262 - Xiaoyong Chen, Douglas L. Maskell:
Supporting multiple-input, multiple-output custom functions in configurable processors. 263-271 - Woo-Chan Park, Cheong-Ghil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han:
A consistency-free memory architecture for sort-last parallel rendering processors. 272-284 - Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert:
Resource efficiency of the GigaNetIC chip multiprocessor architecture. 285-299 - Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich:
Efficient control generation for mapping nested loop programs onto processor arrays. 300-309 - Sunil Kim, Jun-Yong Lee:
A system architecture for high-speed deep packet inspection in signature-based network intrusion prevention. 310-320 - Ralf Salomon, Frank Sill:
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective. 321-327 - Sébastien Lafond, Johan Lilius:
Energy consumption analysis for two embedded Java virtual machines. 328-337
Volume 53, Number 7, July 2007
- Madhura Purnaprajna, Marek Z. Reformat, Witold Pedrycz:
Genetic algorithms for hardware-software partitioning and optimal resource allocation. 339-354 - Alejandro Martínez, Raúl Martínez, Francisco José Alfaro, José L. Sánchez:
A low-cost strategy to provide full QoS support in Advanced Switching networks. 355-368 - J. Jyotheswar, Sudipta Mahapatra:
Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression. 369-378 - Il-Gu Lee, Sok-Kyu Lee:
Efficient automatic gain control algorithm and architecture for wireless LAN receivers. 379-385 - Bernd Scheuermann, Stefan Janson, Martin Middendorf:
Hardware-oriented ant colony optimization. 386-402 - Jochen Hollmann, Anders Ardö, Per Stenström:
Effectiveness of caching in a distributed digital library system. 403-416 - Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. 417-436 - Jung-Shian Li, Chuan-Gang Liu, Cheng-Yu Huang:
Achieving multipoint-to-multipoint fairness with RCNWA. 437-452 - Mozammel H. A. Khan, Marek A. Perkowski:
Quantum ternary parallel adder/subtractor with partially-look-ahead carry. 453-464
Volume 53, Number 8, August 2007
- Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis:
Editorial. 465 - Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll:
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures. 466-476 - Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen:
Benchmarking mesh and hierarchical bus networks in system-on-chip context. 477-488 - Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere:
Exploiting program phase behavior for energy reduction on multi-configuration processors. 489-500 - Stefan Farfeleder, Andreas Krall, R. Nigel Horspool:
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures. 501-510 - John McAllister, Roger F. Woods, Scott Fischaber, E. Malins:
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. 511-523 - Chunhui Zhang, Yun Long, Fadi J. Kurdahi:
A scalable embedded JPEG 2000 architecture. 524-538 - Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene:
Optimizing data structures at the modeling level in embedded multimedia. 539-549
Volume 53, Number 9, September 2007
- Myungsu Choi, Zachary D. Patitz, Byoungjae Jin, Feng Tao, Nohpill Park, Minsu Choi:
Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony. 551-567 - Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena:
Low power data processing system with self-reconfigurable architecture. 568-576 - Mohammed Akkal, Pepe Siy:
A new Mixed Radix Conversion algorithm MRC-II. 577-586 - Ehsan Atoofian, Amirali Baniasadi:
Speculative trivialization point advancing in high-performance processors. 587-601 - Rafal Kapela, Andrzej Rybarczyk:
Real-time shape description system based on MPEG-7 descriptors. 602-618 - Dajin Wang:
A heuristic fault-tolerant routing algorithm in mesh using rectilinear-monotone polygonal fault blocks. 619-628 - Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez:
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. 629-643 - Jeong-Uk Kang, Jinsoo Kim, Chanik Park, Hyoungjun Park, Joonwon Lee:
A multi-channel architecture for high-performance NAND flash-based storage system. 644-658 - Andrea Santoro, Francesco Quaglia:
Multiprogrammed non-blocking checkpoints in support of optimistic simulation on myrinet clusters. 659-676
Volume 53, Number 10, October 2007
- Timo D. Hämäläinen, Stephan Wong, John Glossner, Stamatis Vassiliadis:
Editorial. 677-678 - Jari Heikkinen, Jarmo Takala:
Effects of program compression. 679-688 - Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll:
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. 689-702 - Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf:
Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. 703-718 - Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
Exploration of distributed shared memory architectures for NoC-based multiprocessors. 719-732 - Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
Efficient design space exploration for application specific systems-on-a-chip. 733-750 - Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich:
Design space exploration of reliable networked embedded systems. 751-763 - Hartwig Jeschke:
Chip size estimation for SOC design space exploration. 764-776 - Stamatis Vassiliadis, Ioannis Sourdis:
FLUX interconnection networks on demand. 777-793
Volume 53, Number 11, November 2007
- Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
Automated memory-aware application distribution for Multi-processor System-on-Chips. 795-815 - Chunlin Li, Layuan Li:
Optimization decomposition approach for layered QoS scheduling in grid computing. 816-832 - Kuei-Chung Chang, Tien-Fu Chen:
Efficient segment-based video transcoding proxy for mobile multimedia services. 833-845 - Ioannis Voyiatzis:
Accumulator-based pseudo-exhaustive two-pattern generation. 846-860 - Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. 861-876 - Wenfa Zhan, Huaguo Liang, Feng Shi, Zhengfeng Huang:
Test data compression scheme based on variable-to-fixed-plus-variable-length coding. 877-887
Volume 53, Number 12, December 2007
- Tae-Sun Chung, Hyung-Seok Park:
STAFF: A flash driver algorithm minimizing block erasures. 889-901 - Huaxi Gu, Jie Zhang, Kun Wang, Zengji Liu, Guochang Kang:
Enhanced fault tolerant routing algorithms using a concept of "balanced ring". 902-912 - John A. Chandy:
Dual actuator logging disk architecture and modeling. 913-926 - Wentong Li, Mehran Rezaei, Krishna M. Kavi, Afrin Naz, Philip H. Sweany:
Feasibility of decoupling memory management from the execution pipeline. 927-936 - Ying-Dar Lin, Kuo-Kun Tseng, Tsern-Huei Lee, Yi-Neng Lin, Chen-Chou Hung, Yuan-Cheng Lai:
A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection. 937-950
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