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Luis M. Ramos
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2020 – today
- 2021
- [j3]Alejandro Valero
, Ruben Gran Tejero
, Darío Suárez Gracia
, Emanuel A. Georgescu, Joaquín Ezpeleta
, Pedro Álvarez
, Adolfo Muñoz
, Luis M. Ramos
, Pablo Ibáñez
:
A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. 156: 38-52 (2021)
2010 – 2019
- 2019
- [c4]Alejandro Valero
, Darío Suárez Gracia, Ruben Gran Tejero
, Luis M. Ramos, Agustín Navarro-Torres
, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo
, Eduardo Montijano, Javier Resano
, María Villarroya-Gaudó, Jesús Alastruey-Benedé
, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez
, Víctor Viñals:
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2011
- [j2]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism 13 (2011)
2000 – 2009
- 2008
- [c3]Luis M. Ramos, José Luis Briz
, Pablo E. Ibáñez
, Víctor Viñals
:
Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336 - 2007
- [j1]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez
, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35(4): 37-44 (2007) - 2006
- [c2]Luis M. Ramos, José Luis Briz
, Pablo E. Ibáñez
, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT 2006: 37-44 - 2000
- [c1]Luis M. Ramos, Pablo E. Ibáñez
, Víctor Viñals
, José M. Llabería
:
Modeling load address behaviour through recurrences. ISPASS 2000: 101-108
Coauthor Index
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