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ORCIDGuido Araujo
Guido Araújo
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- affiliation: University of Campinas (UNICAMP), Institute of Computing, Sao Paulo, Brazil
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Journal Articles
- 2024
[j41]Lucas Morais
, Carlos Álvarez, Daniel Jiménez-González, Juan Miguel De Haro Ruiz, Guido Araujo, Michael Frank, Alfredo Goldman, Xavier Martorell:
Enabling HW-Based Task Scheduling in Large Multicore Architectures. IEEE Trans. Computers 73(1): 138-151 (2024)- 2023
- [j40]Samuel Cajahuaringa, Daniel L. Z. Caetano, Leandro N. Zanotto, Guido Araujo, Munir S. Skaf:
MassCCS: A High-Performance Collision Cross-Section Software for Large Macromolecular Assemblies. J. Chem. Inf. Model. 63(11): 3557-3566 (2023) - [j39]Catalina Munoz Morales, Bruno C. Honorio, Joao P. L. de Carvalho, Alexandro Baldassin, Guido Araujo:
On the impact of mode transition on phased transactional memory performance. J. Parallel Distributed Comput. 173: 126-139 (2023) - [j38]Rafael C. F. Sousa, Márcio Machado Pereira, Yongin Kwon, Taeho Kim, Namsoon Jung, Chang Soo Kim, Michael Frank, Guido Araujo:
Tensor slicing and optimization for multicore NPUs. J. Parallel Distributed Comput. 175: 66-79 (2023) - [j37]Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral:
Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering. Softw. Pract. Exp. 53(9): 1793-1814 (2023) - [j36]Vinicius Espindola, Luciano G. Zago, Hervé Yviquel, Guido Araujo:
Source Matching and Rewriting for MLIR Using String-Based Automata. ACM Trans. Archit. Code Optim. 20(2): 22:1-22:26 (2023) - [j35]Victor Ferrari, Rafael Cardoso Fernandes Sousa, Márcio Machado Pereira, Joao P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo:
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions. ACM Trans. Archit. Code Optim. 20(4): 54:1-54:26 (2023) - 2022
- [j34]Guido Araujo, Lucas Wanner:
Special Issue on Compiling for Accelerators. IEEE Micro 42(5): 6-8 (2022) - [j33]Bruno Chinelato Honorio, João P. L. de Carvalho, Catalina Munoz Morales, Alexandro Baldassin, Guido Araujo:
Using Barrier Elision to Improve Transactional Code Generation. ACM Trans. Archit. Code Optim. 19(3): 46:1-46:23 (2022) - 2021
- [j32]João P. L. de Carvalho, Braedy Kuzma, Ivan Korostelev, José Nelson Amaral, Christopher Barton, José E. Moreira, Guido Araujo:
KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls. ACM Trans. Archit. Code Optim. 18(3): 38:1-38:22 (2021) - 2019
- [j31]Rafael C. F. Sousa, Márcio Machado Pereira, Fernando Magno Quintão Pereira, Guido Araujo:
Data-flow analysis and optimization for data coherence in heterogeneous architectures. J. Parallel Distributed Comput. 130: 126-139 (2019) - [j30]Joao P. L. de Carvalho, Guido Araujo, Alexandro Baldassin:
The Case for Phase-Based Transactional Memory. IEEE Trans. Parallel Distributed Syst. 30(2): 459-472 (2019) - 2018
- [j29]Leandro Zanotto, Gabriel Heerdt, Paulo C. T. Souza, Guido Araujo, Munir S. Skaf:
High performance collision cross section calculation - HPCCS. J. Comput. Chem. 39(21): 1675-1681 (2018) - [j28]Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo:
CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence. Microprocess. Microsystems 60: 185-195 (2018) - [j27]Hervé Yviquel, Lauro Cruz, Guido Araujo:
Cluster Programming using the OpenMP Accelerator Model. ACM Trans. Archit. Code Optim. 15(3): 35:1-35:23 (2018) - [j26]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. IEEE Trans. Parallel Distributed Syst. 29(2): 466-480 (2018) - 2017
- [j25]Gleison Souza Diniz Mendonca, Breno Campos Ferreira Guimarães, Péricles Alves, Márcio Machado Pereira, Guido Araujo, Fernando Magno Quintão Pereira:
DawnCC: Automatic Annotation for Data Parallelism and Offloading. ACM Trans. Archit. Code Optim. 14(2): 13:1-13:25 (2017) - 2016
- [j24]Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo:
Study of hardware transactional memory characteristics and serialization policies on Haswell. Parallel Comput. 54: 46-58 (2016) - 2015
- [j23]Guido Araujo, Jean-Luc Gaudiot, Manish Parashar, Derek Chiou, José Nelson Amaral, Chita R. Das:
Guest Editorial: SBAC-PAD 2013. Int. J. Parallel Program. 43(6): 961-964 (2015) - 2014
- [j22]Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu:
Microcode Compression Using Structured-Constrained Clustering. Int. J. Parallel Program. 42(1): 140-164 (2014) - 2013
- [j21]Daniel Nicácio, Alexandro Baldassin, Guido Araujo:
Transaction Scheduling Using Dynamic Conflict Avoidance. Int. J. Parallel Program. 41(1): 89-110 (2013) - [j20]André Loureiro, João Paulo Porto, Guido Araujo:
Extending decoupled software pipeline to parallelize Java programs. Softw. Pract. Exp. 43(5): 525-541 (2013) - 2012
- [j19]Bruno C. Albertini, Sandro Rigo, Guido Araujo:
Computational reflection and its application to platform verification. Des. Autom. Embed. Syst. 16(1): 1-17 (2012) - [j18]Reinaldo A. Bergamaschi, Leonardo Piga, Sandro Rigo, Rodolfo Azevedo, Guido Araújo:
Data center power and performance optimization through global selection of P-states and utilization rates. Sustain. Comput. Informatics Syst. 2(4): 198-208 (2012) - 2009
- [j17]Alexandro Baldassin, Felipe Klein, Guido Araujo, Rodolfo Azevedo, Paulo Centoducatte:
Characterizing the Energy Consumption of Software Transactional Memory. IEEE Comput. Archit. Lett. 8(2): 56-59 (2009) - [j16]Felipe Klein, Roberto Leao, Guido Araujo, Luiz C. V. dos Santos, Rodolfo Azevedo:
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 660-673 (2009) - 2008
- [j15]Ricardo Santos, Rodolfo Azevedo, Guido Araujo:
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor. J. Univers. Comput. Sci. 14(21): 3465-3480 (2008) - 2007
- [j14]Marcio Juliato, Guido Araujo, Julio César López-Hernández, Ricardo Dahab:
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. J. VLSI Signal Process. 47(1): 59-76 (2007) - 2006
- [j13]Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers:
Offset assignment using simultaneous variable coalescing. ACM Trans. Embed. Comput. Syst. 5(4): 864-883 (2006) - 2005
- [j12]Guido Araujo, Edna Barros, Elmar U. K. Melcher, Rodolfo Azevedo, Karina R. G. da Silva, Bruno O. Prado, Manoel Eusébio de Lima:
A SystemC-only design methodology and the CINE-IP multimedia platform. Des. Autom. Embed. Syst. 10(2-3): 181-202 (2005) - [j11]Cristiano C. de Araújo, Millena Gomes, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
Platform designer: An approach for modeling multiprocessor platforms based on SystemC. Des. Autom. Embed. Syst. 10(4): 253-283 (2005) - [j10]Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araújo, Edna Barros:
The ArchC Architecture Description Language and Tools. Int. J. Parallel Program. 33(5): 453-484 (2005) - [j9]Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano:
The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. ACM J. Exp. Algorithmics 10 (2005) - [j8]Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo:
Dynamic binary control-flow errors detection. SIGARCH Comput. Archit. News 33(5): 15-20 (2005) - [j7]Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo:
Efficient datapath merging for partially reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 969-980 (2005) - 2004
- [j6]Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo:
The design of dynamically reconfigurable datapath coprocessors. ACM Trans. Embed. Comput. Syst. 3(2): 361-384 (2004) - 2003
- [j5]Guilherme Ottoni, Guido Araujo:
Address register allocation for arrays in loops of embedded programs. Microelectron. J. 34(11): 1009-1018 (2003) - 2002
- [j4]Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra:
Global array reference allocation. ACM Trans. Design Autom. Electr. Syst. 7(2): 336-357 (2002) - 2001
- [j3]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1319-1328 (2001) - 2000
- [j2]Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain:
Expression-tree-based algorithms for code compression on embedded RISC architectures. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 530-533 (2000) - 1998
- [j1]Guido Araujo, Sharad Malik:
Code generation for fixed-point DSPs. ACM Trans. Design Autom. Electr. Syst. 3(2): 136-161 (1998)
Conference and Workshop Papers
- 2022
- [c90]Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, Guido Araujo:
Improving Convolution via Cache Hierarchy Tiling and Reduced Packing. PACT 2022: 538-539 - [c89]Hervé Yviquel, Márcio Machado Pereira, Emilio Francesquini, Guilherme Valarini, Gustavo Leite, Pedro Henrique Di Francia Rosso, Rodrigo Ceccato, Carla Cusihualpa, Vitoria Dias, Sandro Rigo, Alan Souza, Guido Araujo:
The OpenMP Cluster Programming Model. ICPP Workshops 2022: 17:1-17:11 - [c88]Carla Cardoso, Hervé Yviquel, Guilherme Valarini, Gustavo Leite, Rodrigo Ceccato, Márcio Machado Pereira, Alan Souza, Guido Araujo:
An OpenMP-only Linear Algebra Library for Distributed Architectures. SBAC-PADW 2022: 17-24 - [c87]Rodrigo Ceccato, Hervé Yviquel, Márcio Machado Pereira, Alan Souza, Guido Araujo:
Implementing the Broadcast Operation in a Distributed Task-based Runtime. SBAC-PADW 2022: 25-32 - [c86]Samuel Cajahuaringa, Leandro N. Zanotto, Daniel L. Z. Caetano, Sandro Rigo, Hervé Yviquel, Munir S. Skaf, Guido Araujo:
Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization. SBAC-PAD 2022: 150-159 - 2021
- [c85]Catalina Munoz Morales, Rafael Murari, Joao P. L. de Carvalho, Bruno Chinelato Honorio, Alexandro Baldassin, Guido Araujo:
Accelerating Graph Applications Using Phased Transactional Memory. Euro-Par 2021: 421-434 - [c84]Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Márcio Machado Pereira, Hervé Yviquel, Guido Araujo:
Enabling OpenMP Task Parallelism on Multi-FPGAs. FCCM 2021: 260 - [c83]Caio S. Rohwedder, João P. L. de Carvalho, José Nelson Amaral, Guido Araújo, Giancarlo Colmenares, Kai-Ting Amy Wang:
Pooling Acceleration in the DaVinci Architecture Using Im2col and Col2im Instructions. IPDPS Workshops 2021: 46-55 - [c82]Catalina Munoz Morales, Bruno C. Honorio, Alexandro Baldassin, Guido Araujo:
Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation. SBAC-PAD 2021: 44-53 - [c81]Rafael C. F. Sousa, Byungmin Jung, Jaehwa Kwak, Michael Frank, Guido Araujo:
Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling. SBAC-PAD 2021: 84-93 - 2020
- [c80]Alexandro Baldassin, Rafael Murari, João P. L. de Carvalho, Guido Araujo, Daniel Castro, João Barreto, Paolo Romano:
NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. Euro-Par 2020: 477-492 - [c79]João P. L. de Carvalho, Bruno C. Honorio, Alexandro Baldassin, Guido Araujo:
Improving Transactional Code Generation via Variable Annotation and Barrier Elision. IPDPS 2020: 1008-1017 - [c78]Bruno Chinelato Honorio, João P. L. de Carvalho, Munir S. Skaf, Guido Araujo:
Using OpenMP to Detect and Speculate Dynamic DOALL Loops. IWOMP 2020: 231-246 - [c77]Vitoria Pinho, Hervé Yviquel, Márcio Machado Pereira, Guido Araujo:
OmpTracing: Easy Profiling of OpenMP Programs. SBAC-PAD 2020: 249-256 - [c76]João P. L. de Carvalho, Braedy Kuzma, Guido Araujo:
Acceleration Opportunities in Linear Algebra Applications via Idiom Recognition. ICPE Companion 2020: 34-35 - 2019
- [c75]Caio Hoffman, Catherine H. Gebotys, Diego F. Aranha, Mario Lúcio Côrtes, Guido Araújo:
Circumventing Uniqueness of XOR Arbiter PUFs. DSD 2019: 222-229 - [c74]Lucas Morais, Vitor Silva, Alfredo Goldman, Carlos Álvarez, Jaume Bosch, Michael Frank, Guido Araujo:
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. MICRO 2019: 861-872 - 2018
- [c73]Pedro Ramos, Gleison Souza Diniz Mendonca, Divino Soares, Guido Araújo, Fernando Magno Quintão Pereira:
Automatic annotation of tasks in structured code. PACT 2018: 31:1-31:13 - [c72]Ciro Ceissler, Ramon Nepomuceno, Márcio Machado Pereira, Guido Araujo:
Automatic Offloading of Cluster Accelerators. FCCM 2018: 224 - [c71]Luis Mattos, Divino Cesar S. Lucas, Juan Salamanca, Joao P. L. de Carvalho, Márcio Machado Pereira, Guido Araujo:
DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability. SBAC-PAD 2018: 29-32 - [c70]Matheus Mortatti, Hervé Yviquel, Guido Araujo:
Automatic Ray-Tracer Cloud Offloading in OPENMP. SBAC-PAD 2018: 428-435 - 2017
- [c69]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. Euro-Par 2017: 607-621 - [c68]Hervé Yviquel, Guido Araujo:
The Cloud as an OpenMP Offloading Device. ICPP 2017: 352-361 - [c67]Joao P. L. de Carvalho, Guido Araujo, Alexandro Baldassin:
Revisiting phased transactional memory. ICS 2017: 25:1-25:10 - [c66]Márcio Machado Pereira, Rafael C. F. Sousa, Guido Araujo:
Compiling and Optimizing OpenMP 4.X Programs to OpenCL and SPIR. IWOMP 2017: 48-61 - [c65]Rafael Cardoso Fernandes Sousa, Márcio Machado Pereira, Fernando Magno Quintão Pereira, Guido Araujo:
Data Coherence Analysis and Optimization for Heterogeneous Computing. SBAC-PAD 2017: 9-16 - [c64]Maicol Zegarra, Márcio Machado Pereira, Xavier Martorell, Guido Araujo:
Automatic Scan Parallelization in OpenMP. SBAC-PAD (Workshops) 2017: 85-90 - 2016
- [c63]Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo:
Cylindrical Reconvergence Physical Unclonable Function. DSD 2016: 446-453 - [c62]Tamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana:
Task parallel programming model + hardware acceleration = performance advantage. Hot Chips Symposium 2016: 1 - [c61]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. IPDPS 2016: 586-595 - [c60]Gleison Souza Diniz Mendonca, Breno Campos Ferreira Guimarães, Péricles Rafael Oliveira Alves, Fernando Magno Quintão Pereira, Márcio Machado Pereira, Guido Araujo:
Automatic Insertion of Copy Annotation in Data-Parallel Programs. SBAC-PAD 2016: 34-41 - [c59]Felipe A. Louza, Simon Gog, Leandro Zanotto, Guido Araujo, Guilherme P. Telles:
Parallel Computation for the All-Pairs Suffix-Prefix Problem. SPIRE 2016: 122-132 - 2015
- [c58]Caio Hoffman, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo:
Computer security by hardware-intrinsic authentication. CODES+ISSS 2015: 143-152 - [c57]Divino Cesar S. Lucas, Guido Araujo:
The Batched DOACROSS loop parallelization algorithm. HPCS 2015: 476-483 - [c56]Alexandro Baldassin, Edson Borin, Guido Araujo:
Performance implications of dynamic memory allocators on transactional memory systems. PPoPP 2015: 87-96 - [c55]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware Transactional Memory to Enable Speculative Trace Optimization. SBAC-PAD (Workshops) 2015: 1-6 - [c54]Matthew Gaudet, Guido Araujo, José Nelson Amaral:
Serialization Management for Best-Effort Hardware Transactional Memory. SBAC-PAD 2015: 138-145 - [c53]Jefferson Capovilla, Mario Lúcio Côrtes, Guido Araujo:
Improving the Statistical Variability of Delay-based Physical Unclonable Functions. SBCCI 2015: 41:1-41:7 - 2014
- [c52]Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo:
Wear-out analysis of Error Correction Techniques in Phase-Change Memory. DATE 2014: 1-4 - [c51]Márcio Machado Pereira, José Nelson Amaral, Guido Araujo:
Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling. ICPP 2014: 141-150 - [c50]Juan Salamanca, Luis Mattos, Guido Araujo:
Loop-Carried Dependence Verification in OpenMP. IWOMP 2014: 87-102 - [c49]Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo:
Multi-dimensional Evaluation of Haswell's Transactional Memory Performance. SBAC-PAD 2014: 144-151 - [c48]Rodolfo Wottrich, Rodolfo Azevedo, Guido Araujo:
Cloud-based OpenMP Parallelization Using a MapReduce Runtime. SBAC-PAD 2014: 334-341 - 2013
- [c47]Andre Baixo, João Paulo Porto, Guido Araujo:
Cache-based cross-iteration coherence for speculative parallelization. HiPC 2013: 216-225 - [c46]Márcio Machado Pereira, Alexandro Baldassin, Guido Araujo, Luiz Eduardo Buzato:
Transaction scheduling using conflict avoidance and Contention Intensity. HiPC 2013: 236-245 - [c45]Divino Cesar S. Lucas, Rafael Auler, Rafael Dalibera, Sandro Rigo, Edson Borin, Guido Araujo:
Modeling virtual machines misprediction overhead. IISWC 2013: 153-162 - 2012
- [c44]Divino Cesar S. Lucas, Guido Araujo, Edson Borin:
Exploring Dynamic Program Behavior with Frames and Phases. WSCAD-SSC 2012: 118-125 - 2011
- [c43]Daniel Nicácio, Alexandro Baldassin, Guido Araujo:
LUTS: A Lightweight User-Level Transaction Scheduler. ICA3PP (1) 2011: 144-157 - [c42]Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu:
Structure-Constrained Microcode Compression. SBAC-PAD 2011: 104-111 - 2010
- [c41]Roberto Gallo, Henrique Kawakami, Ricardo Dahab, Rafael Azevedo, Saulo Lima, Guido Araujo:
T-DRE: a hardware trusted computing base for direct recording electronic vote machines. ACSAC 2010: 191-198 - [c40]Daniel Nicácio, Guido Araujo:
Reducing False Aborts in STM Systems. ICA3PP (1) 2010: 499-510 - [c39]João Paulo Porto, Guido Araujo, Edson Borin, Youfeng Wu:
Trace Execution Automata in Dynamic Binary Translation. ISCA Workshops 2010: 99-116 - [c38]Maxwell Souza, Daniel Nicácio, Guido Araujo:
ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation. ISCA Workshops 2010: 117-138 - 2009
- [c37]Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo:
On the energy-efficiency of software transactional memory. SBCCI 2009 - 2007
- [c36]Bruno C. Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araújo, Edna Barros, Willians Azevedo:
A computational reflection mechanism to support platform debugging in SystemC. CODES+ISSS 2007: 81-86 - [c35]Fabio Augusto Cappabianco, Guido Araujo, Alexandre X. Falcão:
The Image Forest Transform Architecture. FPT 2007: 137-144 - [c34]Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos:
A multi-model power estimation engine for accuracy optimization. ISLPED 2007: 280-285 - [c33]Richard Maciel, Bruno C. Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo:
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. ISVLSI 2007: 351-356 - [c32]Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos:
On the Limitations of Power Macromodeling Techniques. ISVLSI 2007: 395-400 - [c31]Fernando Kronbauer, Alexandro Baldassin, Bruno C. Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo:
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. IEEE International Workshop on Rapid System Prototyping 2007: 123-129 - 2006
- [c30]Ricardo Santos, Rodolfo Azevedo, Guido Araujo:
2D-VLIW: An Architecture Based on the Geometry of Computation. ASAP 2006: 87-94 - [c29]Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo:
Software-Based Transparent and Comprehensive Control-Flow Error Detection. CGO 2006: 333-345 - [c28]Edson Borin, Maurício Breternitz Jr., Youfeng Wu, Guido Araujo:
Clustering-Based Microcode Compression. ICCD 2006: 189-196 - [c27]Ricardo Santos, Rodolfo Azevedo, Guido Araujo:
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. IPDPS 2006 - 2005
- [c26]Cristiano C. de Araújo, Edna Barros, Rodolfo Azevedo, Guido Araujo:
Processor Centric Specification and Modelling of MPSoCs. FDL 2005: 303-315 - [c25]Marcio Juliato, Guido Araujo, Julio César López-Hernández, Ricardo Dahab:
A custom instruction approach for hardware and software implementations of finite field arithmetic over F263 using Gaussian normal bases. FPT 2005: 5-12 - [c24]Felipe Klein, Rodolfo Azevedo, Guido Araujo:
High-Level Switching Activity Prediction Through Sampled Monitored Simulation. SoC 2005: 161-166 - [c23]Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto:
Design of a decompressor engine on a SPARC processor. SBCCI 2005: 110-114 - 2004
- [c22]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Multi-profile based code compression. DAC 2004: 244-249 - [c21]Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735 - [c20]Edson Borin, Felipe Klein, Nahri Moreano, Rodolfo Azevedo, Guido Araujo:
Fast instruction set custornization. ESTIMedia 2004: 53-58 - [c19]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Multi-Profile Instruction Based Compression. SBAC-PAD 2004: 23-29 - [c18]Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo:
ArchC: A SystemC-Based Architecture Description Language. SBAC-PAD 2004: 66-73 - [c17]Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo:
Optimizations for Compiled Simulation Using Instruction Type Information. SBAC-PAD 2004: 74-81 - [c16]Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta:
An automatic testbench generation tool for a SystemC functional verification methodology. SBCCI 2004: 66-70 - [c15]Sandro Rigo, Marcio Juliato, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte:
Teaching computer architecture using an architecture description language. WCAE 2004: 6 - [c14]Cid C. de Souza, André M. Lima, Nahri Moreano, Guido Araujo:
The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation. WEA 2004: 545-558 - 2003
- [c13]Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Mixed static/dynamic profiling for dictionary based code compression. SoC 2003: 159-163 - [c12]Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo:
Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9 - [c11]Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers:
Improving Offset Assignment through Simultaneous Variable Coalescing. SCOPES 2003: 285-297 - 2002
- [c10]Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano:
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ISSS 2002: 38-43 - 2001
- [c9]Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. CASES 2001: 141-148 - [c8]Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik:
Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC 2001: 274-288 - 2000
- [c7]Marcelo Silva Cintra, Guido Araujo:
Array Reference Allocation Using SSA-Form and Live Range Growth. LCTES 2000: 48-62 - 1999
- [c6]Paulo Centoducatte, Ricardo Pannain, Guido Araujo:
Compressed Code Execution on DSP Architectures. ISSS 1999: 56-63 - 1998
- [c5]Guido Araujo, Paulo Centoducatte, Mario Lúcio Côrtes, Ricardo Pannain:
Code Compression Based on Operand Factorization. MICRO 1998: 194-201 - 1996
- [c4]Guido Araujo, Sharad Malik, Mike Tien-Chien Lee:
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC 1996: 591-596 - [c3]Guido Araujo, Ashok Sudarsanam, Sharad Malik:
Instruction Set Design and Optimizations for Address Computation in DSP Architectures. ISSS 1996: 102-107 - 1995
- [c2]Guido Araujo, Sharad Malik:
Optimal code generation for embedded memory non-homogeneous register architectures. ISSS 1995: 36-41 - 1994
- [c1]Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang:
Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64
Editorship
- 2010
- [e1]João Antonio Martino, Guido Araujo, Alex Orailoglu, Felipe Klein:
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010. ACM 2010, ISBN 978-1-4503-0152-7 [contents]
Informal and Other Publications
- 2023
- [i6]Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo:
Advancing Direct Convolution using Convolution Slicing Optimization and ISA Extensions. CoRR abs/2303.04739 (2023) - [i5]Rafael C. F. Sousa, Márcio Machado Pereira, Yongin Kwon, Taeho Kim, Namsoon Jung, Chang Soo Kim, Michael Frank, Guido Araujo:
Tensor Slicing and Optimization for Multicore NPUs. CoRR abs/2304.03013 (2023) - [i4]Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral:
Fast Matrix Multiplication via Compiler-only Layered Data Reorganization and Intrinsic Lowering. CoRR abs/2305.18236 (2023) - 2022
- [i3]Vinicius Couto, Luciano G. Zago, Hervé Yviquel, Guido Araújo:
Source Matching and Rewriting. CoRR abs/2202.04153 (2022) - [i2]Hervé Yviquel, Márcio Machado Pereira, Emilio Francesquini, Guilherme Valarini, Gustavo Leite, Pedro Henrique Di Francia Rosso, Rodrigo Ceccato, Carla Cusihualpa, Vitoria Dias, Sandro Rigo, Alan Souza, Guido Araujo:
The OpenMP Cluster Programming Model. CoRR abs/2207.05677 (2022) - 2021
- [i1]Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Márcio Machado Pereira, Hervé Yviquel, Guido Araujo:
Enabling OpenMP Task Parallelism on Multi-FPGAs. CoRR abs/2103.10573 (2021)
Coauthor Index
João P. L. de Carvalho
aka: Joao P. L. de Carvalho
aka: Joao P. L. de Carvalho
Rafael C. F. Sousa
aka: Rafael Cardoso Fernandes Sousa
aka: Rafael Cardoso Fernandes Sousa
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